MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 28

• Manufacturer Part Number: MT8VDDT6432UY-5K1
• Description: MODULE DDR 256MB 100-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6432UY-5K1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 100-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Initialization
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
10. Wait at least
11. Using the LMR command program the Mode Register to set operating parameters
12. Wait at least
13. Issue a PRECHARGE ALL command.
14. Wait at least
15. Issue an AUTO REFRESH command (Note this may be moved prior to step 13).
16. Wait at least
17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13).
18. Wait at least
19. Although not required by the Micron device, JEDEC requires a LMR command to clear
20. Wait at least
21. At this point the DRAM is ready for any valid command. Note 200 clock cycles are
1. Simultaneously apply power to V
2. Apply V
3. Assert and hold CKE at a LVCMOS logic low.
4. Provide stable CLOCK signals.
5. Wait at least 200µs.
6. Bring CKE high and provide at least one NOP or DESELECT command. At this point
7. Perform a PRECHARGE ALL command.
8. Wait at least
9. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the
To ensure device operation the DRAM must be initialized as described below:
the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a
SSTL_2 input unless a power cycle occurs.
DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set
to 0; where n = most significant bit).
and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset
and any READ command.
the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters
should be utilized as in step 11.
required between step 11 (DLL Reset) and any READ command.
REF
and then V
t
t
t
t
t
t
t
RP time, during this time NOPs or DESELECT commands must be given.
MRD time, only NOPs or DESELECT commands are allowed.
MRD time, only NOPs or DESELECT commands are allowed.
RP time, only NOPs or DESELECT commands are allowed.
RFC time, only NOPs or DESELECT commands are allowed.
RFC time, only NOPs or DESELECT commands are allowed.
MRD time, only NOPs or DESELECT commands are allowed.
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
TT
power.
28
DD
and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q.
©2004, 2005 Micron Technology, Inc. All rights reserved.
Initialization