MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 30

• Manufacturer Part Number: MT8VDDT6432UY-5K1
• Description: MODULE DDR 256MB 100-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6432UY-5K1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 100-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Presence Detect
SPD Clock and Data Conventions
SPD Start Condition
SPD Stop Condition
SPD Acknowledge
Figure 11:
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
Data Validity
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11,
Data Validity, and Figure 12, Definition of Start and Stop).
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 13, Acknowledge Response
From Receiver).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each sub-
sequent eight-bit word. In the read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
SDA
SCL
DATA STABLE
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
DATA
CHANGE
30
DATA STABLE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Serial Presence Detect
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