LFDAS12XSCT Freescale Semiconductor, LFDAS12XSCT Datasheet - Page 105

• Manufacturer Part Number: LFDAS12XSCT
• Description: HARDWARE MC9S12XS 48-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSCT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

1
2.3.44
Freescale Semiconductor
Address 0x025A
Read: Anytime.
Write: Anytime.
DDRP
DDRP
DDRP
DDRP
Field
Reset
6-3
2,0
7
1
W
R
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. If the PWM shutdown feature is enabled this
pin is forced to be an input. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not
change.
1 Associated pin configured as output
0 Associated pin configured as input
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an
output for a timer port associated with an enabled output compare. Else depending on the configuration of the
enabled SCI the I/O state will be forced to be input or output. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an
output for a timer port associated with an enabled output compare. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
DDRP7
Port P Data Direction Register (DDRP)
0
7
DDRP6
0
6
Figure 2-42. Port P Data Direction Register (DDRP)
Table 2-41. DDRP Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
DDRP5
0
5
DDRP4
0
4
Description
DDRP3
3
0
DDRP2
0
Port Integration Module (S12XSPIMV1)
2
DDRP1
Access: User read/write
0
1
DDRP0
0
0
105
1