LFDAS12XSCT Freescale Semiconductor, LFDAS12XSCT Datasheet - Page 82

• Manufacturer Part Number: LFDAS12XSCT
• Description: HARDWARE MC9S12XS 48-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSCT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

1
Port Integration Module (S12XSPIMV1)
2.3.13
82
Address 0x001D (PRR)
NCLKX2
NECLK
Read: Always reads 0x00
Write: Unimplemented
DIV16
Field
EDIV
Reset
4-0
7
6
5
W
R
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3, ...
11111 ECLK rate = bus clock rate divided by 32
PIM Reserved Register
0
0
7
= Unimplemented or Reserved
0
0
6
Table 2-12. ECLKCTL Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
Figure 2-11. PIM Reserved Register
0
0
5
0
0
4
Description
3
0
0
0
0
2
Freescale Semiconductor
0
0
1
Access: User read
0
0
0
1