LFDAS12XSCT Freescale Semiconductor, LFDAS12XSCT Datasheet - Page 221

• Manufacturer Part Number: LFDAS12XSCT
• Description: HARDWARE MC9S12XS 48-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSCT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is
generated, thus the breakpoint does not occur at the tagged instruction boundary.
6.4.5.1.3
Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point
the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the
address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.
6.4.5.2
The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in
the DBGTCR register. The modes are described in the following subsections. The trace buffer organization
is shown in
6.4.5.2.1
In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored.
COF addresses are defined as follows :
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
Change-of-flow addresses stored include the full 23-bit address bus of CPU12X and an information byte,
which contains a source/destination bit to indicate whether the stored address was a source address or
destination address.
MARK1
MARK2
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Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
Destination address of indexed JMP, JSR, and CALL instruction
Destination address of RTI, RTS, and RTC instructions.
Vector address of interrupts, except for SWI and BDM vectors
LDX
JMP
NOP
Table
Trace Modes
Storing with End-Trigger
Normal Mode
When an CPU12X COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets exectuted after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
6-40.
#SUB_1
0,X
S12XS Family Reference Manual, Rev. 1.11
; IRQ interrupt occurs during execution of this
;
NOTE
S12X Debug (S12XDBGV3) Module
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