LFDAS12XSCT Freescale Semiconductor, LFDAS12XSCT Datasheet - Page 164

• Manufacturer Part Number: LFDAS12XSCT
• Description: HARDWARE MC9S12XS 48-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSCT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

Interrupt (S12XINTV2)
4.4.5
The XINT module supports three system reset exception request types (for details please refer to the Clock
and Reset Generator module (CRG)):
4.4.6
The priority (from highest to lowest) and address of all exception vectors issued by the XINT module upon
request by the CPU is shown in
than maskable interrupts. Please note that between the three software interrupts (Unimplemented op-code
trap request, SWI/BGND request, SYS request) there is no real priority defined because they cannot occur
simultaneously (the S12XCPU executes one instruction at a time).
1
2
3
164
16 bits vector address based
only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor
only implemented if device features a Memory Protection Unit (MPU)
1. Pin reset, power-on reset, low-voltage reset, or illegal address reset
2. Clock monitor reset request
3. COP watchdog reset request
(Vector base + 0x00F8)
(Vector base + 0x00F6)
(Vector base + 0x0012)
(Vector base + 0x0018)
(Vector base + 0x0016)
(Vector base + 0x0014)
(Vector base + 0x00F4)
(Vector base + 0x00F2)
(Vector base + 0x0010)
Vector Address
0x00F0–0x001A)
(Vector base +
0xFFFC
0xFFFE
0xFFFA
Reset Exception Requests
Exception Priority
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0010)).
1
Pin reset, power-on reset, low-voltage reset, illegal address reset
Clock monitor reset
COP watchdog reset
Unimplemented op-code trap
Software interrupt instruction (SWI) or BDM vector request
System call interrupt instruction (SYS)
(reserved for future use)
XGATE Access violation interrupt request
CPU Access violation interrupt request
XIRQ interrupt request
IRQ interrupt request
Device specific I bit maskable interrupt sources (priority determined by the associated
configuration registers, in descending order)
Spurious interrupt
Table 4-10. Exception Vector Map and Priority
Table
S12XS Family Reference Manual, Rev. 1.11
4-10. Generally, all non-maskable interrupts have higher priorities
NOTE
3
2
Source
Freescale Semiconductor