LFDAS12XSFT Freescale Semiconductor, LFDAS12XSFT Datasheet - Page 379

• Manufacturer Part Number: LFDAS12XSFT
• Description: HARDWARE MC9S12XS 80-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSFT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

Read: Always read $00 in normal modes
Write: Unimplemented in normal modes
13.3.2.12 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.
The counter can be read at any time without affecting the count or the operation of the PWM channel. In
left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned
output mode, the counter counts from 0 up to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. The counter is also cleared at the end of the effective period (see
Section 13.4.2.5, “Left Aligned Outputs”
details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the
PWMCNTx register. For more detailed information on the operation of the counters, see
“PWM Timer
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Read: Anytime
Freescale Semiconductor
Module Base + 0x000A, 0x000B
Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3
Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7
Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.
Reset
Reset
W
W
R
R
Bit 7
0
0
0
0
7
7
Counters”.
Writing to these registers when in special modes can alter the PWM
functionality.
= Unimplemented or Reserved
Figure 13-14. PWM Channel Counter Registers (PWMCNTx)
0
0
0
0
6
6
6
Figure 13-13. Reserved Registers (PWMSCNTx)
S12XS Family Reference Manual, Rev. 1.11
0
0
0
0
5
5
5
and
Section 13.4.2.6, “Center Aligned Outputs”
NOTE
NOTE
0
0
0
0
4
4
4
0
0
0
0
3
3
3
Pulse-Width Modulator (S12PWM8B8CV1)
0
0
0
0
2
2
2
0
0
0
0
1
1
1
Section 13.4.2.4,
for more
Bit 0
0
0
0
0
0
0
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