LFDAS12XSFT Freescale Semiconductor, LFDAS12XSFT Datasheet - Page 439

• Manufacturer Part Number: LFDAS12XSFT
• Description: HARDWARE MC9S12XS 80-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSFT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

15.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
15.3.2.1
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base +0x0000
Reset
SPTIE
MSTR
CPOL
CPHA
Field
SPIE
SPE
7
6
5
4
3
2
W
R
Register Descriptions
SPIE
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
SPI Control Register 1 (SPICR1)
0
7
SPE
0
6
Figure 15-3. SPI Control Register 1 (SPICR1)
S12XS Family Reference Manual, Rev. 1.11
Table 15-2. SPICR1 Field Descriptions
SPTIE
0
5
MSTR
0
4
Description
CPOL
0
3
CPHA
1
2
Serial Peripheral Interface (S12SPIV5)
SSOE
0
1
LSBFE
0
0
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