DC-VIDEO-TVP5146N Altera, DC-VIDEO-TVP5146N Datasheet

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... CCPGM V I/O pre-driver power supply CCPD V I/O power supply CCIO © July 2010 Altera Corporation 1. Stratix III Device Datasheet: DC and Switching Characteristics III devices. Electrical characteristics include operating conditions ® may cause permanent damage to the device. Additionally, device (Note 1) (Part Parameter ...

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... A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.2 V can only be at 4.2 V for 15.8% over the lifetime of the device; for a device lifetime of 10 years, this is equivalent to 15.8% of ten years which is 18.96 months. ...

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... Table 1–2: (1) This input voltage is regardless of the V Recommended Operating Conditions This section lists the functional operation limits for AC and DC parameters for Stratix III devices. from Stratix III devices. All supplies are required to monotonically reach their full-rail values within t Table 1–3. Recommended Operating Conditions for Stratix III Devices (Part ...

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... For the EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, the industrial junction temperature range is from 0° 100° C, regardless of supply voltage. (3) Altera recommends a 3.0-V nominal battery voltage when connecting V security key, you may connect the V CCBAT Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Conditions — — — — ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics DC Characteristics This section lists the input pin capacitances, on-chip termination tolerance, and hot- socketing specifications. Supply Current Standby current is the current the device draws after the device is configured with no inputs/outputs toggling and no activity in the device. Because these currents vary largely with the resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design ...

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... V and 1 Row I/O. S  (3) 1.5 V and 1.2 V only supports 40- to 60- (4) For resistance tolerance after power-up calibration, refer to Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1.2 V 1.5 V 1.8 V Min Max Min ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics The accuracy listed in temperature changes, the termination resistance value varies. resistance tolerance for Stratix III OCT. Table 1–8. On-Chip Termination Resistance Tolerance Specification for Stratix III Devices Symbol Description Internal series termination without ...

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... Table 1–11: (1) The I/O ramp rate more. For ramp rates faster than 10 ns, |I capacitance and dv/dt is the slew rate. Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics (Note 1) V CCIO Parameter Input capacitance on top and bottom I/O pins ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Internal Weak Pull-Up Resistor Table 1–12 lists the weak pull-up resistor values for Stratix III devices. Table 1–12. Internal Weak Pull-Up Resistor for Stratix III Devices Symbol Value of the I/O pin pull- ...

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... V -0.1 V REF REF CLASS II HSTL-12 -0.15 V -0.08 V REF REF CLASS I Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics for voltage referenced receiver input waveform and Table 1–14. V (V) REF Min Typ Max CCIO CCIO 0.833 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Table 1–15. Single-Ended SSTL and HSTL I/O Standards Signal Specifications V (V) I/O IL(DC) Standard Min Max Min HSTL-12 -0.15 V -0.08 V +0.08 REF REF CLASS II Note to Table 1–15: (1) Use the current strength settings that are equal or larger than the I OCT or lower current strengths may provide better signal integrity and lower power. Refer to the figures for “ ...

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... Use the EPE and PowerPlay Power Analyzer for current estimates of remaining power supplies. f For more information about power estimation tools, refer to the Estimator User Guide For Stratix III FPGAs the Quartus II Handbook. Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics V (V) (1) V (V) ID ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Switching Characteristics This section provides performance characteristics of Stratix III core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary and Final and each designation is defined below. Preliminary—Preliminary characteristics are created using simulation results, process data, and other known parameters. Final— ...

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Table 1–20. PLL Specifications for Stratix III Devices (Part Symbol Parameter f Input clock frequency IN f Input frequency to the PFD INPFD f PLL VCO operating range VCO Input clock or external feedback t EINDUTY clock ...

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... Period Jitter for dedicated clock output (F < 100 MHz) OUT Cycle to Cycle Jitter for dedicated clock output 100 MHz) (F OUT t (5) OUTCCJ_DC Cycle to Cycle Jitter for dedicated clock output (F < 100 MHz) OUT Period Jitter for clock output on  100 MHz) regular IO (F OUT t ...

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... OUTCCJ_IO Cycle to Cycle Jitter for clock output on regular IO (F <100 MHz) OUT Period Jitter for dedicated clock t (5), CASC_OUTPJ_DC  output in cascaded PLLs (F (7) OUT 100 MHz) Period Jitter for dedicated clock output in cascaded PLLs (F OUT 100 MHz) Frequency drift after PFDENA is f disabled for duration of 100  ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics DSP Block Specifications Table 1–21 lists the Stratix III DSP block performance specifications. Table 1–21. DSP Block Performance Specifications for Stratix III Devices Number of Mode Multipliers 99-bit multiplier ( (2) 99-bit multiplier ( (2) 12 ...

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... ROM 1P, 1K × 9, 512 × 18, or 256 × 36 ROM 2P, 8K × × × 4 ROM 2P, 1K × 512 × 18 Min Pulse Width (Clock High Time) Min Pulse Width (Clock Low Time) Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C2 ( TriMatrix ALUTs ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1–22. TriMatrix Memory Block Performance Specifications for Stratix III Devices Memory Block Mode Type True dual-port 16K × × 18 True dual-port 4K × 36 Simple dual-port 16K × × 18 Simple dual-port 4K × × ...

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... Remote Update feature. For more information, refer to the max Update Circuitry (ALTREMOTE_UPDATE) Megafunction User (2) The data rate must be 4× slower than the clock when you use decompression and/or encryption. (3) For more information about the minimum and typical DCLK F the Configuring Stratix III Devices Table 1–24 lists the JTAG timing parameters and values for Stratix III devices. Refer to the figure for “ ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Periphery Performance This section describes periphery performance, including high-speed I/O and external memory interface. I/O performance supports several system interfacing, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. For ...

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... SERDES factor ( Uses an SDR Register DPA — — DPA run length Soft CDR mode Soft-CDR PPM — — tolerance Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics (Note 1), (2) C2 C3, I3 — 311 (4) — 200 (4) — 160 — ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1–25. True and Emulated LVDS Specifications for Stratix III Devices Symbol Conditions Non DPA Mode — — Sampling Window Notes to Table 1–25: (1) When 10, the SERDES block is used. (2) When the SERDES block is bypassed. ...

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... DPA time specification with DPA PLL calibration enabled. Figure 1–2. DPA Lock Time Specification with DPA PLL Calibration Enabled rx_reset rx_dpa_locked Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics (Note 1), (2), Number of repetitions per 256 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Figure 1–3 shows the LVDS Soft-CDR/ DPA sinusoidal jitter tolerance specifications for Stratix III devices. Figure 1–3. LVDS Soft-CDR/DPA Sinusiodal Jitter Tolerance Specification for Stratix III Devices Table 1–27 lists the LVDS Soft-CDR/ DPA sinusiodal jitter mask values for Stratix III devices. Table 1– ...

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... Column I/Os and Row I/Os of the device. (2) For implementation, refer to the “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” section in the Interfaces in Stratix III Devices chapter. Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics (Note ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1–29. Transmitter Channel-to-Channel Skew (TCCS)—Write Side I/O Memory Type Standard DDR3 SDRAM (with 1.5-V Deskew circuitry, SSTL 401 MHz–533 MHz) DDR3 SDRAM (8-tap 1.5-V phase offset, SSTL 375 MHz–400 MHz) DDR3 SDRAM (8-tap 1 ...

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... Note to Table 1–30: (1) “Low” indicates a 6-bit DQS delay setting; “high” indicates a 5-bit DQS delay setting. Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics (Note 1.1 V CCL ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1–31 lists the average DQS phase offset delay per setting for Stratix III devices. Table 1–31. Average DQS Phase Offset Delay per Setting for Stratix III Devices Speed Grade C2 C3, I3 ...

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... Output Duty Cycle Note to Table 1–35: (1) The DCD specification applies to clock outputs from the PLLs, global clock tree, and IOE driving dedicated and general-purpose I/O pins. I/O Timing The following sections describe the timing models, preliminary and final timings, I/O timing measurement methodology, I/O default capacitive loading, programmable IOE delay, programmable output buffer delay, user I/O timing, and dedicated clock pin timing ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Preliminary and Final Timing Timing models can have either preliminary or final status. The Quartus II software issues an informational message during design compilation if the timing models are preliminary. Table 1–36 Preliminary status means that the timing models are subject to change in future Quartus II releases ...

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... Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to V Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Input Data Delay Input Clock Delay ) at worst-case process, minimum voltage, and ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 5. Compare the results of steps 2 and 4. The increase or decrease in delay must be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace. The Quartus II software reports the timing with the conditions listed in using Equation 1– ...

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... CLASS II 1.8-V Differential — — HSTL CLASS I 1.8-V Differential — — HSTL CLASS II 1.5-V Differential — — HSTL CLASS I Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Loading and Termination CCIO CCPD CC — — 3.135 3 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–37. Output Timing Measurement Methodology for Output Pins (Part I/O Standard 1.5-V Differential — — HSTL CLASS II 1.2-V Differential — — HSTL CLASS I 1.2-V Differential — — HSTL CLASS II LVDS — ...

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... SSTL-18 CLASS II 1.5-V HSTL CLASS I 1.5-V HSTL CLASS II 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.2-V HSTL Differential SSTL-2 CLASS I Differential SSTL-2 CLASS II Differential SSTL-18 CLASS I Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Loading and Termination CCIO ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–38. Default Loading of Various I/O Standards for Stratix III Devices (Part Differential SSTL-18 CLASS II 1.8-V Differential HSTL CLASS I 1.8-V Differential HSTL CLASS II 1.5-V Differential HSTL CLASS I 1.5-V Differential HSTL CLASS II 1 ...

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... GCLK su PLL t 1.237 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics (Note 1) Parameter 0 (default) Rising and/or Falling Edge delay Table 1–140 list user I/O pin timing for Stratix III devices. I/O are reported for the cases when the I/O clock is driven by a ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–41. EP3SL50 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t -0.701 su GCLK t 0.827 3.0-V h LVCMOS t -0.986 GCLK su PLL t 1.237 h t -0.696 su GCLK t 0.822 h 2 -0.981 ...

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... GCLK t 0.827 3.0-V h PCI-X t -0.986 GCLK su PLL t 1.237 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.607 -0.903 -0.990 -1.084 -1.037 -1.398 -0.990 -1.084 -1.037 -1.398 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–42 lists the EP3SL50 row pins input timing parameters for single-ended I/O standards. Table 1–42. EP3SL50 Row Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t -0.884 ...

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... PLL t 1.003 h t 0.904 su GCLK 1.5-V t -0.655 h HSTL t -0.890 GCLK CLASS II su PLL t 1.003 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.860 1.692 1.930 2.146 2.032 0.971 1 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–42. EP3SL50 Row Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t 0.904 su GCLK 1.2-V t -0.655 h HSTL t -0.884 GCLK CLASS I su PLL t 0.997 h t 0.910 su GCLK 1.2 ...

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... LVTTL GCLK 2.985 t co 12mA GCLK 3.341 t co PLL GCLK 2.967 t co 16mA GCLK 3.323 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.156 4.382 4 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–43. EP3SL50 Column Pins output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial GCLK 3.046 t co 4mA GCLK 3.402 t co PLL GCLK 2.967 t co 8mA GCLK 3.323 t co PLL 3 ...

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... PLL GCLK 3.002 t co 10mA GCLK 3.358 t co PLL GCLK 2.997 t co 12mA GCLK 3.353 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.347 4.782 5 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–43. EP3SL50 Column Pins output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial GCLK 3.221 t co 2mA GCLK 3.577 t co PLL GCLK 3.098 t co 4mA GCLK 3.454 t co PLL 1 ...

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... GCLK 3.353 t co PLL SSTL-15 CLASS II GCLK 3.000 t co 16mA GCLK 3.356 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 2.988 4.233 4 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–43. EP3SL50 Column Pins output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial GCLK 3.007 t co 4mA GCLK 3.363 t co PLL GCLK 3.000 t co 6mA GCLK 3.356 t co ...

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... PCI GCLK 3.477 t co PLL GCLK 3.121 t co 3.0-V — GCLK PCI-X 3.477 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.003 4 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–44 lists the EP3SL50 row pins output timing parameters for single-ended I/O standards. Table 1–44. EP3SL50 Row Pins output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial 3.197 ...

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... GCLK t co 12mA GCLK 1.325 t co PLL GCLK 2.994 t co SSTL-2 16mA GCLK CLASS II 1.316 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.667 5.251 5 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–44. EP3SL50 Row Pins output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial 3.047 GCLK t co 4mA GCLK 1.316 t co PLL 3.042 GCLK t co 6mA GCLK 1.311 t co PLL 3 ...

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... PCI — GCLK 1.436 t co PLL GCLK 3.114 t co 3.0-V — GCLK PCI-X 1.436 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.256 4 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–45 through devices for differential I/O standards. Table 1–45 lists the EP3SL50 column pins input timing parameters for differential I/O standards. Table 1–45. EP3SL50 Column Pins Input Timing Parameters (Part ...

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... GCLK DIFFERENTIAL 0.822 t h 2.5-V SSTL 1.135 t GCLK CLASS II su PLL -0.884 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.740 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–46 lists the EP3SL50 row pins input timing parameters for differential I/O standards. Table 1–46. EP3SL50 Row Pins Input Timing Parameters (Part Fast Model I/O Standard Clock Industrial -0.919 t su GCLK 1 ...

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... GCLK DIFFERENTIAL 0.872 t h 2.5-V 1.045 t SSTL CLASS II GCLK su PLL -0.795 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.788 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–47 lists the EP3SL50 column pins output timing parameters for differential I/O standards. Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial Commercial 3.029 GCLK t co LVDS_E_1R — ...

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... PLL 3.029 GCLK t DIFFERENTIAL co 1.8-V HSTL 16mA GCLK 3.025 t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.286 4.658 5.066 5.583 5.443 5.661 5.193 5.710 5.572 5.729 3 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK 3.056 t co 4mA GCLK 3.046 t co PLL 3.046 GCLK t co 6mA GCLK 3.039 t co PLL DIFFERENTIAL 3 ...

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... GCLK LVDS_E_3R 3.080 t co PLL GCLK 3.096 t co RSDS — GCLK 3.085 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.258 4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 3 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK 3.082 t co RSDS_E_1R — GCLK 3.093 t co PLL GCLK 3.083 t co RSDS_E_3R — GCLK 3.069 t co PLL GCLK 3 ...

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... SSTL CLASS I co PLL GCLK 3.066 t DIFFERENTIAL co 2.5-V 12mA GCLK 3.094 t SSTL CLASS I co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 2.842 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 3 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK 3.076 t DIFFERENTIAL co 2.5-V 16mA GCLK 3.062 t SSTL CLASS II co PLL Table 1–49 and must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock ...

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... GCLK t 0.902 h 1 -0.931 GCLK su PLL t 1.184 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Table 1–54 list the maximum I/O timing parameters for EP3SL70 CCL CCL CCL CCL 1.1 V 1.1 V 1 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–51. EP3SL70 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t -0.749 su GCLK t 0.873 SSTL-2 h CLASS I t -0.902 GCLK su PLL t 1.155 h t -0.749 su GCLK t 0.873 SSTL-2 ...

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... PLL t -0.688 h t -0.817 su GCLK t 0.931 h 3.0-V LVTTL t 0.931 GCLK su PLL t -0.682 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.731 -1.050 -1.145 -1.085 -1.037 -1.416 -1.145 -1.085 -1.037 -1.416 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–52. EP3SL70 Row Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t -0.817 su GCLK t 0.931 3.0-V h LVCMOS t 0.931 GCLK su PLL t -0.682 h t -0.805 su GCLK t 0.919 h 2 0.943 ...

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... GCLK t -0.682 3.0-V h PCI-X t -0.817 GCLK su PLL t 0.931 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 0.990 -1.105 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–53 lists the EP3SL70 column pins output timing parameters for single-ended I/O standards. Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part Fast Model I/O Clock Standard Industrial GCLK 3.187 ...

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... GCLK 3.045 t co 12mA GCLK 3.370 t co PLL GCLK 3.006 t co 16mA GCLK 3.332 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.067 4.284 4.635 5.091 4.971 5.177 4.635 5.091 4.971 5.177 3 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part Fast Model I/O Clock Standard Industrial GCLK 3.378 t co 2mA GCLK 3.705 t co PLL GCLK 3.200 t co 4mA GCLK 3.524 t co PLL GCLK 3 ...

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... GCLK 3.013 t co 10mA GCLK 3.340 t co PLL GCLK 3.013 t co 12mA GCLK 3.340 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.240 4.665 5.087 5.624 5.503 5.711 5.087 5.624 5.503 5.711 3 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part Fast Model I/O Clock Standard Industrial GCLK 3.020 t co 8mA GCLK 3.346 t co PLL SSTL-18 CLASS II GCLK 3.022 t co 16mA GCLK 3.349 ...

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... GCLK 3.344 t co PLL GCLK 3.014 t 1.5-V co HSTL 16mA GCLK 3.342 t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.026 4.261 4.619 5.085 4.964 5.172 4.619 5.085 4.964 5.172 3 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part Fast Model I/O Clock Standard Industrial GCLK 3.035 t co 4mA GCLK 3.361 t co PLL GCLK 3.026 t co 6mA GCLK 3.353 t co PLL GCLK 3 ...

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... V 8mA GCLK 1.376 t co PLL 3.006 GCLK t co 12mA GCLK 1.319 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.424 4.767 5.163 5.668 5.532 5.739 5.293 5.802 5.667 5.813 1 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–54. EP3SL70 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.350 t co 2mA GCLK 1.728 t co PLL 3.177 GCLK t co 4mA GCLK 1.503 t co PLL 1.8 V 3.102 ...

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... SSTL-15 6mA GCLK CLASS I 1.312 t co PLL 3.011 GCLK t co 8mA GCLK 1.295 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.269 4.613 4.993 5.503 5.367 5.579 5.126 5.638 5.503 5.649 1 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–54. EP3SL70 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.021 t co 4mA GCLK 1.314 t co PLL 3.014 GCLK t co 6mA GCLK 1.302 t co PLL 3.005 GCLK 1 ...

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... GCLK DIFFERENTIAL 0.822 t h 1.8-V HSTL 1.135 t GCLK CLASS I su PLL -0.884 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Table 1–60 list the maximum I/O timing parameters for EP3SL70 CCL CCL CCL CCL Commercial 1 ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–55. EP3SL70 Column Pins Input Timing Parameters (Part Fast Model I/O Standard Clock Industrial -0.717 t su GCLK DIFFERENTIAL 0.834 t h 1.8-V HSTL 1.123 t GCLK CLASS II su PLL -0.872 t h -0.717 ...

Page 84

... GCLK DIFFERENTIAL 0.873 t h 1.8-V 1.054 t HSTL CLASS I GCLK su PLL -0.804 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.939 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 1 ...

Page 85

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–56. EP3SL70 Row Pins Input Timing Parameters (Part Fast Model I/O Standard Clock Industrial Commercial -0.757 t su GCLK DIFFERENTIAL 0.873 t h 1.8-V 1.054 t HSTL CLASS II GCLK su PLL -0.804 t h -0.743 ...

Page 86

... GCLK 3.031 t co PLL 3.031 DIFFERENTIAL GCLK t co 1.2-V HSTL 16mA GCLK 3.035 t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.246 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 3 ...

Page 87

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial 3.061 GCLK t co 4mA GCLK 3.047 t co PLL 3.035 GCLK t co 6mA GCLK 3.035 t co PLL GCLK 3.031 ...

Page 88

... GCLK 3.064 t 1.8-V SSTL co PLL CLASS II 3.053 GCLK t co 16mA GCLK 3.048 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.279 4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 3 ...

Page 89

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial 3.034 GCLK t co 8mA GCLK 3.032 t co PLL 3.036 DIFFERENTIAL GCLK t co 2.5-V SSTL 10mA GCLK 3.036 t CLASS I ...

Page 90

... HSTL CLASS I co PLL GCLK 3.117 t DIFFERENTIAL co 4mA 1.5-V GCLK 3.102 t HSTL CLASS I co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 2.842 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 3 ...

Page 91

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK 3.091 t DIFFERENTIAL co 1.5-V 6mA GCLK 3.071 t HSTL CLASS I co PLL GCLK 3.068 t DIFFERENTIAL co 8mA 1.5-V GCLK 3 ...

Page 92

... Commercial 0.158 0.168 RCLK input adder -0.014 -0.012 RCLK PLL input adder -0.114 -0.116 RCLK output adder 1.642 1.675 RCLK PLL output adder Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1 ...

Page 93

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–60 lists the EP3SL70 row pin delay adders when using the regional clock. Table 1–60. EP3SL70 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial RCLK input adder ...

Page 94

... GCLK t 0.973 1.8-V HSTL h CLASS I t -1.154 GCLK su PLL t 1.434 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.943 -1.381 -1.502 -1.698 -1.643 -1.996 -1.502 -1.698 -1.643 -1.996 1 ...

Page 95

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–61. EP3SL110 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t -0.846 su GCLK t 0.984 1.8-V HSTL h CLASS II t -1.165 GCLK su PLL t 1.445 h t -0.846 su GCLK t 0.984 1 ...

Page 96

... GCLK t 0.920 h 1 1.038 GCLK su PLL t -0.786 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 1.1 V -0.883 -1.252 -1.441 -1.559 -1.604 -1.843 -1.465 -1.551 -1.605 -1.881 1 ...

Page 97

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–62. EP3SL110 Row Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial t -0.847 su GCLK t 0.963 SSTL-2 h CLASS I t 1.055 GCLK su PLL t -0.803 h t -0.847 su GCLK t 0.963 SSTL-2 h CLASS ...

Page 98

... GCLK 3.676 t co PLL GCLK 3.279 t co 16mA GCLK 3.669 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V -0.795 -1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639 ...

Page 99

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.445 t co 4mA GCLK 3.835 t co PLL GCLK 3.290 t co 8mA GCLK 3.680 t co PLL 3.3-V LVCMOS GCLK 3 ...

Page 100

... GCLK 3.674 t co PLL GCLK 3.266 t co 12mA GCLK 3.656 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.439 4.846 5.240 5.749 5.619 5.912 5.240 5.749 5.619 5.912 3 ...

Page 101

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.576 t co 2mA GCLK 3.966 t co PLL GCLK 3.364 t co 4mA GCLK 3.754 t co PLL GCLK 3.339 ...

Page 102

... GCLK 3.659 t co PLL GCLK 3.266 t co 12mA GCLK 3.656 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.270 4.616 4.998 5.494 5.363 5.657 4.998 5.494 5.363 5.657 3 ...

Page 103

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.268 t co 8mA GCLK 3.658 t co PLL SSTL-15 CLASS II GCLK 3.271 t co 16mA GCLK 3.661 t co PLL GCLK 3 ...

Page 104

... GCLK 3.782 t co PLL GCLK 3.392 t co 3.0-V — GCLK PCI-X 3.782 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.267 4.605 4.987 5.483 5.352 5.646 4.987 5.483 5.352 5.646 3 ...

Page 105

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–64 lists the EP3SL110 row pins output timing parameters for single-ended I/O standards. Table 1–64. EP3SL110 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial 3.182 GCLK t co 4mA GCLK 1 ...

Page 106

... GCLK 1.254 t co PLL 3.017 GCLK t co SSTL-2 16mA GCLK CLASS II 1.238 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.706 5.298 5.747 6.303 6.177 6.439 5.888 6.445 6.318 6.538 1 ...

Page 107

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–64. EP3SL110 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial 3.049 GCLK t co 4mA GCLK 1.281 t co PLL 3.034 GCLK t co 6mA GCLK 1.266 t co PLL 3.023 GCLK ...

Page 108

... GCLK 1.351 t co PLL 3.137 GCLK t co 3.0-V — GCLK PCI-X 1.351 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.256 4.603 4.987 5.478 5.352 5.614 5.105 5.597 5.470 5.690 1 ...

Page 109

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–65 through devices for differential I/O standards. Table 1–65 lists the EP3SL110 column pins input timing parameters for differential I/O standards. Table 1–65. EP3SL110 Column Pins Input Timing Parameters (Part ...

Page 110

... I/O Standard Clock Industrial Commercial -0.919 t su GCLK 1.043 t h LVDS 0.959 t GCLK su PLL -0.698 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.852 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 ...

Page 111

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–66. EP3SL110 Row Pins Input Timing Parameters (Part Fast Model I/O Standard Clock Industrial Commercial -0.919 t su GCLK 1.043 t h MINI-LVDS 0.959 t GCLK su PLL -0.698 t h -0.919 t su GCLK 1.043 ...

Page 112

... MINI- — GCLK LVDS_E_1R 1.308 t co PLL 3.096 GCLK t co MINI- — GCLK LVDS_E_3R 1.304 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.777 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 ...

Page 113

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial 3.100 GCLK t co RSDS_E_1R — GCLK 1.308 t co PLL 3.096 GCLK t co RSDS_E_3R — GCLK 1.304 t co PLL GCLK 3 ...

Page 114

... DIFFERENTIAL 8mA GCLK 1.314 t 1.5-V SSTL co PLL CLASS II 3.107 GCLK t co 16mA GCLK 1.315 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.353 4.737 5.133 5.643 5.504 5.788 5.256 5.765 5.629 5.862 1 ...

Page 115

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial 3.135 GCLK t co 4mA GCLK 1.343 t co PLL 3.124 GCLK t co 6mA GCLK 1.332 t co PLL DIFFERENTIAL GCLK 3 ...

Page 116

... HSTL CLASS I co PLL GCLK 3.130 t DIFFERENTIAL co 1.5-V 4mA GCLK 1.350 t HSTL CLASS I co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 2.894 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1 ...

Page 117

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–68. EP3SL110 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK 3.119 t DIFFERENTIAL co 1.5-V 6mA GCLK 1.339 t HSTL CLASS I co PLL GCLK 3.116 t DIFFERENTIAL co 1.5-V 8mA GCLK 1.336 ...

Page 118

... Fast Model Parameter Industrial Commercial 0.186 RCLK input adder RCLK PLL input adder 2.391 -0.374 RCLK output adder RCLK PLL output adder -2.001 Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1 ...

Page 119

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–70 lists the EP3SL110 row pin delay adders when using the regional clock. Table 1–70. EP3SL110 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial 0.086 RCLK input adder ...

Page 120

... GCLK t 1.041 1.8-V HSTL h CLASS I t -1.198 GCLK su PLL t 1.478 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V -0.992 -1.450 -1.608 -1.813 -1.794 -2.122 -1.608 -1.813 -1.794 -2.122 1 ...

Page 121

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–71. EP3SL150 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial t -0.917 su GCLK t 1.052 1.8-V HSTL h CLASS II t -1.209 GCLK su PLL t 1.489 h t -0.917 su GCLK t 1.052 1.5-V HSTL ...

Page 122

... GCLK t 0.995 h 1 1.034 GCLK su PLL t -0.782 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 1.1 V -0.964 -1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993 1 ...

Page 123

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–72. EP3SL150 Row Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial t -0.862 su GCLK t 0.978 SSTL-2 h CLASS I t 1.051 GCLK su PLL t -0.799 h t -0.862 su GCLK t 0.978 SSTL-2 h CLASS ...

Page 124

... GCLK 3.692 t co PLL GCLK 3.262 t co 16mA GCLK 3.685 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V -0.877 -1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 1 ...

Page 125

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.428 t co 4mA GCLK 3.901 t co PLL GCLK 3.273 t co 8mA GCLK 3.701 t co PLL 3.3-V LVCMOS GCLK 3 ...

Page 126

... GCLK 3.267 t co 10mA GCLK 3.690 t co PLL GCLK 3.249 t co 12mA GCLK 3.672 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.439 4.846 5.222 5 ...

Page 127

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.559 t co 2mA GCLK 4.069 t co PLL GCLK 3.347 t co 4mA GCLK 3.786 t co PLL GCLK 3.322 ...

Page 128

... GCLK 3.252 t co 10mA GCLK 3.675 t co PLL GCLK 3.249 t co 12mA GCLK 3.672 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.270 4.615 4.980 5 ...

Page 129

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.251 t co 8mA GCLK 3.674 t co PLL SSTL-15 CLASS II GCLK 3.254 t co 16mA GCLK 3.677 t co PLL GCLK 3 ...

Page 130

... PCI — GCLK 3.798 t co PLL GCLK 3.375 t co 3.0-V — GCLK PCI-X 3.798 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.267 4.605 4 ...

Page 131

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–74 lists the EP3SL150 row pins output timing parameters for single-ended I/O standards. Table 1–74. EP3SL150 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial 3.214 GCLK t co 4mA GCLK 1 ...

Page 132

... GCLK 1.264 t co PLL 3.022 GCLK t co SSTL-2 16mA GCLK CLASS II 1.255 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.699 5.291 5.740 6.296 6.169 6.434 5.882 6.438 6.310 6.534 1 ...

Page 133

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–74. EP3SL150 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial 3.042 GCLK t co 4mA GCLK 1.276 t co PLL 3.027 GCLK t co 6mA GCLK 1.271 t co PLL 3.016 GCLK ...

Page 134

... GCLK 1.375 t co PLL 3.142 GCLK t co 3.0-V — GCLK PCI-X 1.375 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.249 4.596 5.002 5.481 5.366 5.616 5.099 5.599 5.484 5.692 1 ...

Page 135

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–75 through devices for differential I/O standards. Table 1–75 lists the EP3SL150 column pins input timing parameters for differential I/O standards. Table 1–75. EP3SL150 Column Pins Input Timing Parameters (Part ...

Page 136

... GCLK DIFFERENTIAL 0.940 t h 2.5-V SSTL 1.124 t GCLK CLASS II su PLL -0.871 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.852 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 ...

Page 137

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–76 lists the EP3SL150 row pins input timing parameters for differential I/O standards. Table 1–76. EP3SL150 Row Pins Input Timing Parameters (Part Fast Model I/O Standard Clock Industrial -0.919 t su GCLK 1 ...

Page 138

... GCLK DIFFERENTIAL 0.873 t h 2.5-V 1.122 t GCLK SSTL CLASS II su PLL -0.868 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.789 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659 ...

Page 139

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–77 lists the EP3SL150 column pins output timing parameters for differential I/O standards. Table 1–77. EP3SL150 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK t co LVDS_E_1R — ...

Page 140

... GCLK t co PLL DIFFERENTIAL GCLK t co 1.8-V HSTL 16mA GCLK t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.121 3.356 4.741 5.138 5.649 5.510 5.794 5.260 5.770 5.634 5.867 1 ...

Page 141

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–77. EP3SL150 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK t co 4mA GCLK t co PLL GCLK t co 6mA GCLK t co PLL DIFFERENTIAL GCLK t 1.5-V SSTL co 8mA GCLK ...

Page 142

... GCLK t co PLL GCLK DIFFERENTIAL t co 2.5-V SSTL 16mA GCLK t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.123 3.360 4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881 1 ...

Page 143

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–78 lists the EP3SL150 row pins output timing parameters for differential I/O standards. Table 1–78. EP3SL150 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK 2.711 t co — ...

Page 144

... GCLK 1.343 t SSTL CLASS I co PLL GCLK 3.106 t co 8mA GCLK 1.326 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.372 4.769 5.171 5.680 5.544 5.799 5.296 5.808 5.671 5.874 1 ...

Page 145

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–78. EP3SL150 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK 3.151 t co 4mA GCLK 1.371 t co PLL GCLK 3.136 t co 6mA GCLK 1.356 t co PLL GCLK 3.125 ...

Page 146

... GCLK t 1.285 3.3-V h LVCMOS t -1.465 GCLK su PLL t 1.778 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Table 1–80 list the EP3SL150 regional clock (RCLK) adder values that CCL CCL CCL CCL 1.1 V 1 ...

Page 147

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–81. EP3SL200 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t -1.148 su GCLK t 1.296 3.0-V h LVTTL t -1.476 GCLK su PLL t 1.789 h t -1.148 su GCLK t 1.296 3.0-V h LVCMOS t -1 ...

Page 148

... PLL t 1.688 h t -1.043 su GCLK t 1.193 h 3.0-V PCI t -1.373 GCLK su PLL t 1.688 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.104 -1.717 -1.673 -1.794 -1.724 -2.272 -1.673 -1.794 1 ...

Page 149

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–81. EP3SL200 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial t -1.148 su GCLK t 1.296 3.0-V h PCI-X t -1.476 GCLK su PLL t 1.789 h Table 1–82 lists the EP3SL200 row pins input timing parameters for single-ended I/O standards. Table 1– ...

Page 150

... GCLK su PLL t 1.347 h t -1.203 su GCLK t 1.010 1.8-V HSTL h CLASS II t 1.338 GCLK su PLL t -1.203 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 0.913 2.151 2.164 2.422 2.330 1 ...

Page 151

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–82. EP3SL200 Row Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial t 1.010 su GCLK t 1.338 1.5-V HSTL h CLASS I t -1.304 GCLK su PLL t 1.438 h t 0.909 su GCLK t -0.632 1.5-V HSTL ...

Page 152

... GCLK 3.893 t co PLL GCLK 3.476 t co 16mA GCLK 3.875 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.677 5.302 5.492 5.997 5.854 6.259 5.492 5.997 5.854 6.259 4 ...

Page 153

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.555 t co 4mA GCLK 3.954 t co PLL GCLK 3.476 t co 8mA GCLK 3.875 t co PLL 3.0-V LVCMOS GCLK 3 ...

Page 154

... GCLK 3.910 t co PLL GCLK 3.506 t co 12mA GCLK 3.905 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.868 5.701 5.947 6.513 6.370 6.775 5.947 6.513 6.370 6.775 4 ...

Page 155

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.730 t co 2mA GCLK 4.129 t co PLL GCLK 3.607 t co 4mA GCLK 4.006 t co PLL 1.2 V GCLK 3 ...

Page 156

... GCLK 3.905 t co PLL SSTL-15 CLASS II GCLK 3.509 t co 16mA GCLK 3.908 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.509 5.153 5.349 5.858 5.715 6.120 5.349 5.858 5.715 6.120 3 ...

Page 157

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.516 t co 4mA GCLK 3.915 t co PLL GCLK 3.509 t co 6mA GCLK 3.908 t co PLL GCLK 3.501 t 1 ...

Page 158

... PCI GCLK 4.029 t co PLL GCLK 3.630 t co 3.0-V — GCLK PCI-X 4.029 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.524 5.175 5.375 5.888 5.745 6.150 5.375 5.888 5.745 6.150 3 ...

Page 159

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–84 lists the EP3SL200 row pins output timing parameters for single-ended I/O standards. Table 1–84. EP3SL200 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial 3.639 GCLK t co 4mA GCLK 1 ...

Page 160

... GCLK 1.378 t co PLL 3.449 GCLK t co SSTL-2 16mA GCLK CLASS II 1.369 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 4.170 6.174 6.451 7.093 6.933 7.278 6.617 7.250 6.933 7.278 2 ...

Page 161

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–84. EP3SL200 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.474 t co 4mA GCLK 1.406 t co PLL 3.465 GCLK t co 6mA GCLK 1.391 t co PLL 3.454 GCLK ...

Page 162

... GCLK 1.489 t co PLL 3.569 GCLK t co 3.0-V — GCLK PCI-X 1.489 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.720 5.479 5.692 6.268 6.108 6.453 5.839 6.402 6.108 6.453 1 ...

Page 163

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–85 through devices for differential I/O standards. Table 1–85 lists the EP3SL200 column pins input timing parameters for differential I/O standards. Table 1–85. EP3SL200 Column Pins Input Timing Parameters (Part ...

Page 164

... GCLK DIFFERENTIAL 1.297 t h 2.5-V SSTL 1.095 t GCLK CLASS II su PLL -0.816 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.244 -1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 1 ...

Page 165

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–86 lists the EP3SL200 row pins input timing parameters for differential I/O standards. Table 1–86. EP3SL200 Row Pins Input Timing Parameters (Part Fast Model I/O Standard Clock Industrial Commercial -1.332 ...

Page 166

... SSTL CLASS I su GCLK 1.306 t h 1.032 t GCLK su PLL -0.751 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.240 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 1 ...

Page 167

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–87 lists the EP3SL200 column pins output timing parameters for differential I/O standards. Table 1–87. EP3SL200 Column Pins output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK t co LVDS_E_1R — ...

Page 168

... GCLK t co PLL GCLK DIFFERENTIAL t co 1.8-V HSTL 16mA GCLK t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.511 3.790 5.589 5.802 6.366 6.202 6.609 5.946 6.509 6.202 6.609 3 ...

Page 169

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–87. EP3SL200 Column Pins output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK t co 4mA GCLK t co PLL GCLK t co 6mA GCLK t co PLL DIFFERENTIAL GCLK t 1.5-V SSTL co 8mA ...

Page 170

... GCLK t co PLL GCLK DIFFERENTIAL t co 2.5-V SSTL 16mA GCLK t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.484 3.762 5.558 5.770 6.334 6.170 6.577 5.915 6.479 6.170 6.577 3 ...

Page 171

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–88 lists the EP3SL200 row pins output timing parameters for differential I/O standards. Table 1–88. EP3SL200 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK 3.152 t co LVDS — ...

Page 172

... GCLK 3.544 t SSTL CLASS I co PLL GCLK 3.560 t co 8mA GCLK 3.549 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.866 5.700 5.916 6.490 6.323 6.702 6.068 6.644 6.323 6.702 3 ...

Page 173

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–88. EP3SL200 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK 3.546 t co 4mA GCLK 3.557 t co PLL GCLK 3.547 t co 6mA GCLK 3.533 t co PLL GCLK 3 ...

Page 174

... GCLK t 1.486 3.3-V h LVCMOS t -1.691 GCLK su PLL t 1.996 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Table 1–90 list the EP3SL200 regional clock (RCLK) adder values that CCL CCL CCL CCL 1.1 V 1 ...

Page 175

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–91. EP3SL340 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial t -1.356 su GCLK t 1.497 h 3.0-V LVTTL t -1.702 GCLK su PLL t 2.007 h t -1.356 su GCLK t 1.497 3.0-V h LVCMOS t -1.702 ...

Page 176

... GCLK t 1.530 h 3.0-V PCI t 0.785 GCLK su PLL t -0.510 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.354 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 1 ...

Page 177

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–91. EP3SL340 Column Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial t -1.356 su GCLK t 1.497 3.0-V h PCI-X t -1.702 GCLK su PLL t 2.007 h Table 1–92 lists the EP3SL340 row pins input timing parameters for single-ended I/O standards. Table 1– ...

Page 178

... GCLK t 1.281 1.8-V HSTL h CLASS II t 0.923 GCLK su PLL t -0.658 h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.332 -1.956 -1.963 -2.136 -2.070 -2.514 -1.972 -2.143 -2.088 -2.556 1 ...

Page 179

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–92. EP3SL340 Row Pins Input Timing Parameters (Part Fast Model I/O Clock Standard Industrial t -1.141 su GCLK t 1.267 1.5-V HSTL h CLASS I t 0.937 GCLK su PLL t -0.672 h t -1.141 su GCLK t 1.267 1.5-V HSTL ...

Page 180

... LVTTL GCLK 3.522 t co 12mA GCLK 4.087 t co PLL GCLK 3.504 t co 16mA GCLK 4.068 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.705 5.372 5.559 6 ...

Page 181

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial GCLK 3.583 t co 4mA GCLK 4.149 t co PLL GCLK 3.504 t co 8mA GCLK 4.070 t co PLL 3 ...

Page 182

... PLL GCLK 3.539 t co 10mA GCLK 4.103 t co PLL GCLK 3.534 t co 12mA GCLK 4.097 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.896 5.772 6.014 6 ...

Page 183

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial GCLK 3.758 t co 2mA GCLK 4.322 t co PLL GCLK 3.635 t co 4mA GCLK 4.200 t co PLL 1 ...

Page 184

... GCLK 4.098 t co PLL SSTL-15 CLASS II GCLK 3.537 t co 16mA GCLK 4.101 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.537 5.223 5.416 5 ...

Page 185

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part Fast Model I/O Clock Standard Industrial Commercial GCLK 3.544 t co 4mA GCLK 4.108 t co PLL GCLK 3.537 t co 6mA GCLK 4.102 t co ...

Page 186

... PCI — GCLK 4.222 t co PLL GCLK 3.658 t co 3.0-V — GCLK PCI-X 4.222 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.552 5 ...

Page 187

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–94 lists the EP3SL340 row pins output timing parameters for single-ended I/O standards. Table 1–94. EP3SL340 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial 3.479 GCLK t co 4mA GCLK 1 ...

Page 188

... GCLK 1.406 t co PLL 3.314 GCLK t co SSTL-2 16mA GCLK CLASS II 1.397 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.942 5.817 6.193 6.841 6.698 7.084 6.248 6.991 6.682 7.186 1 ...

Page 189

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–94. EP3SL340 Row Pins Output Timing Parameters (Part I/O Clock Standard Industrial GCLK 3.375 t co 4mA GCLK 1.418 t co PLL 3.370 GCLK t co 6mA GCLK 1.413 t co PLL 3.359 GCLK ...

Page 190

... PCI — GCLK 1.517 t co PLL 3.434 GCLK t co 3.0-V — GCLK PCI-X 1.517 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.583 5.262 5 ...

Page 191

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–95 through devices for differential I/O standards. Table 1–95 lists the EP3SL340 column pins input timing parameters for differential I/O standards. Table 1–95. EP3SL340 Column Pins Input Timing Parameters (Part ...

Page 192

... GCLK DIFFERENTIAL 1.250 t h 2.5-V SSTL 1.014 t GCLK CLASS II su PLL -0.746 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.181 -1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429 1 ...

Page 193

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–96 lists the EP3SL340 row pins input timing parameters for differential I/O standards. Table 1–96. EP3SL340 Row Pins Input Timing Parameters (Part Fast Model I/O Standard Clock Industrial -1.246 t su GCLK 1 ...

Page 194

... SSTL CLASS I su GCLK 1.210 t h 0.985 t GCLK su PLL -0.718 t h Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.147 -1.725 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304 1 ...

Page 195

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–97 lists the EP3SL340 column pins output timing parameters for differential I/O standards. Table 1–97. EP3SL340 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK t co LVDS_E_1R — ...

Page 196

... GCLK t co PLL DIFFERENTIAL GCLK t co 1.8-V HSTL 16mA GCLK t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.459 3.726 5.469 5.666 6.206 6.054 6.462 5.799 6.338 6.186 6.539 1 ...

Page 197

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–97. EP3SL340 Column Pins Output Timing Parameters (Part I/O Standard Clock Industrial Commercial GCLK t co 4mA GCLK t co PLL GCLK t co 6mA GCLK t co PLL DIFFERENTIAL GCLK t 1.5-V SSTL co 8mA ...

Page 198

... GCLK t co PLL GCLK DIFFERENTIAL t co 2.5-V SSTL 16mA GCLK t CLASS II co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.461 3.730 5.481 5.678 6.219 6.067 6.475 5.813 6.352 6.200 6.553 1 ...

Page 199

... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1–98 lists the EP3SL340 row pins output timing parameters for differential I/O standards. Table 1–98. EP3SL340 Row Pins Output Timing Parameters (Part I/O Standard Clock Industrial GCLK 3.022 t co LVDS — ...

Page 200

... GCLK 1.482 t SSTL CLASS I co PLL GCLK 3.414 t co 8mA GCLK 1.465 t co PLL Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.708 5.456 5.652 6.194 6.041 6.418 5.789 6.327 6.177 6.497 1 ...