DC-VIDEO-TVP5146N Altera, DC-VIDEO-TVP5146N Datasheet - Page 330
DC-VIDEO-TVP5146N
Manufacturer Part Number
DC-VIDEO-TVP5146N
Description
VIDEO DAUGHTER CARD
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.DC-VIDEO-TVP5146N.pdf
(58 pages)
Specifications of DC-VIDEO-TVP5146N
Main Purpose
Video, Daughter Card
Embedded
No
Utilized Ic / Part
Altera Dev Kits
Primary Attributes
Dual Composite Video Input - NTSC or PAL
Secondary Attributes
10-bit BT.656 Output, Compatible with Expansion Connector, Standard on Most Altera Development Kits
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1704
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- Download datasheet (4Mb)
1–330
Chapter Revision History
Table 1–202. Chapter Revision History (Part 1 of 2)
Stratix III Device Handbook, Volume 2
July 2010
March 2010
July 2009
May 2009
February 2009
October 2008
Date
Table 1–202
Version
2.3
2.2
2.1
2.0
1.9
1.8
lists the revision history for this chapter.
Updated
Updated for the Quartus II software version 9.1 SP2 release:
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Minor text edits.
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Updated Table 1–7, Table 1–8, Table 1–11, Table 1–19, Table 1–23,
Table 1–25, Table 1–28, Table 1–29, and Table 1–33.
Updated the “Sinusoidal Maximum Allowed Overshoot/Undershoot Voltage”
and “External Memory Interface Specifications” sections.
Minor text edits.
Updated Table 1–1, Table 1–7, Table 1–9, Table 1–18, Table 1–21,
Table 1–22, Table 1–23, Table 1–25, Table 1–26, Table 1–28, Table 1–29,
Table 1–30, Table 1–33, Table 1–35, Table 1–41, Table 1–43, Table 1–51,
Table 1–53, Table 1–61, Table 1–63, Table 1–71, Table 1–73, Table 1–81,
Table 1–83, Table 1–91, Table 1–93, Table 1–101, Table 1–103, Table 1–111,
Table 1–113, Table 1–121, Table 1–123, Table 1–131, and Table 1–133.
Updated Equation 1–1.
Updated “Programmable IOE Delay”, “PLL Specifications”, “DSP Block
Specifications”, “TriMatrix Memory Block Specifications”, “External Memory
Interface Specifications”, and “High-Speed I/O Specifications” sections.
Updated all Timing Information Tables in “User I/O Pin Timing” and
“Dedicated Clock Pin Timing” sections.
Removed “Referenced Documents” and “Maximum Input and Output Toggle
Rate” sections.
Updated “Operating Conditions”.
Added “Bus Hold Specifications”.
Updated Table 1–3, Table 1–6, Table 1–7, Table 1–11, and Table 1–14.
Updated Table 1–17 to Table 1–25.
Updated Table 1–39 to Table 1–47.
Updated Table 1–50 to Table 1–210.
Added (Note 3) to Table 1–11.
Added (Note 1) to Table 1–14.
Added (Note 6) to Table 1–17.
Added (Note 1) to Table 1–47.
Added Table 1–26.
Added Figure 1–2.
Table
1–11,
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Table
1–20,
Changes Made
Table
1–25, and
Table
© July 2010 Altera Corporation
1–33.
Chapter Revision History
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