DP83848K-MAU-EK National Semiconductor, DP83848K-MAU-EK Datasheet - Page 33

• Manufacturer Part Number: DP83848K-MAU-EK
• Description: BOARD EVALUATION DP83848K
• Manufacturer: National Semiconductor

Specifications of DP83848K-MAU-EK

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83848K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Not Compliant

5.2 ESD PROTECTION
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures
need be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo-
nents are less sensitive from ESD events.
See Section 8.0 for ESD rating.
5.3 CLOCK IN (X1) RECOMMENDATIONS
The DP83848K supports an external CMOS level oscillator
source or a crystal resonator device.
Oscillator
If an external clock source is used, X1 should be tied to the
clock source and X2 should be left floating.
The CMOS oscillator specifications for MII Mode are listed
in Table 7.25 MHz Oscillator Specification. For RMII Mode,
the CMOS oscillator specifications are listed in Table 8.50
MHz Oscillator Specification. For RMII mode, it is not rec-
ommended that the system clock out, Pin 21, be used as
the reference clock to the MAC without first verifying the
interface timing. See AN-1405 for more details.
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typi-
1. This limit is provided as a guideline for component selection and not guaranteed by production testing. Refer to
AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,” for details on jitter performance.
Rise / Fall Time
Parameter
Frequency
Frequency
Frequency
Tolerance
Symmetry
Stability
Jitter
Jitter
40%
Min
Table 7. 25 MHz Oscillator Specification
Typ
25
33
cal connection for a crystal resonator circuit. The load
capacitor values will vary with the crystal vendors; check
with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel reso-
nance AT cut crystal with a minimum drive level of 100 W
and a maximum of 500 W. If a crystal is specified for a
lower drive level, a current limiting resistor should be
placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, C
should be set at 33 pF, and R
Specification for 25 MHz crystal are listed in Table 9..
800
800
60%
Max
+50
+50
Figure 12. Crystal Oscillator Circuit
C
6
L1
1
1
X1
Units
nsec
psec
psec
MHz
ppm
ppm
1
should be set at 0
X2
R
Temperature
www.national.com
1 year aging
C
Operational
20% - 80%
Duty Cycle
Condition
Short term
1
Long term
L2
L1
and C
L2