AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 379

• Manufacturer Part Number: AT91SAM9M10-G45-EK
• Description: KIT EVAL FOR AT91SAMG45/9M10
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9M10-G45-EK

• Contents: Board, Cables, Power Supply
• Processor To Be Evaluated: AT91SAM9M10
• Processor Series: AT91SAM9
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, JTAG
• Operating Supply Voltage: 5 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Features: Two High Speed USB Hosts, LCD TFT Display
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9M10,
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9M10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.8.2.3
Figure 27-8.
27.8.2.4
Figure 27-9.
27.8.3
27.8.3.1
6355B–ATARM–21-Jun-10
Normal Interrupt
Internal Interrupt Edge Triggered Source
Internal Interrupt Level Sensitive Source
Priority Controller
Internal Interrupt Edge Triggered Source
Internal Interrupt Level Sensitive Source
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt
conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast
Forcing).
Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writ-
ing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the
highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR
(Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have hap-
pened on other interrupt sources since the nIRQ has been asserted, the priority controller
determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The
read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider
that the interrupt has been taken into account by the software.
The current priority level is defined as the priority level of the current interrupt.
If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read,
the interrupt with the lowest interrupt source number is serviced first.
nIRQ
MCK
nIRQ
MCK
Peripheral Interrupt
Peripheral Interrupt
Becomes Active
Becomes Active
Maximum IRQ Latency = 4.5 Cycles
Maximum IRQ Latency = 3.5 Cycles
AT91SAM9M10
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