AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 886
AT91SAM9M10-G45-EK
Manufacturer Part Number
AT91SAM9M10-G45-EK
Description
KIT EVAL FOR AT91SAMG45/9M10
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Specifications of AT91SAM9M10-G45-EK
Contents
Board, Cables, Power Supply
Processor To Be Evaluated
AT91SAM9M10
Processor Series
AT91SAM9
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, JTAG
Operating Supply Voltage
5 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Features
Two High Speed USB Hosts, LCD TFT Display
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9M10,
Rohs Compliant
Yes
For Use With/related Products
AT91SAM9M10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
INFINEON
Quantity:
10 000
Company:
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
Atmel
Quantity:
135
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38.6.21
Name:
Addresses:
Access:
• CHANN_ENB (Channel Enable Command)
0 = DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by hardware when the chan-
nel source bus is disabled at end of buffer.
If the UDPHS_DMACONTROL register LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to
set the corresponding CHANN_ENB bit to start the described transfer, if needed.
If the UDPHS_DMACONTROL register LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may
then be read and/or written reliably as soon as both UDPHS_DMASTATUS register CHANN_ENB and CHANN_ACT flags
read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the
UDPHS_DMASTATUS register CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
1 = UDPHS_DMASTATUS register CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pend-
ing request will start the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
0 = no channel register is loaded after the end of the channel transfer.
1 = the channel controller loads the next descriptor after the end of the current transfer, i.e. when the
UDPHS_DMASTATUS/CHANN_ENB bit is reset.
If the UDPHS_DMA CONTROL/CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer
request.
DMA Channel Control Command Summary
886
BURST_LCK
LDNXT_DSC
31
23
15
–
7
0
0
1
1
AT91SAM9M10
UDPHS DMA Channel Control Register
DESC_LD_IT
30
22
14
UDPHS_DMACONTROLx [x = 1..5]
0xFFF78328 [1], 0xFFF78338 [2], 0xFFF78348 [3], 0xFFF78358 [4], 0xFFF78368 [5]
Read-write
–
6
CHANN_ENB
0
1
0
1
END_BUFFIT
29
21
13
–
5
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
END_TR_IT
28
20
12
–
4
BUFF_LENGTH
BUFF_LENGTH
Description
END_B_EN
27
19
11
–
3
END_TR_EN
26
18
10
–
2
LDNXT_DSC
25
17
9
–
1
6355B–ATARM–21-Jun-10
CHANN_ENB
24
16
8
–
0
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