OM13000 NXP Semiconductors, OM13000 Datasheet

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OM13000

Manufacturer Part Number
OM13000
Description
BOARD LPCXPRESSO LPC1768
Manufacturer
NXP Semiconductors
Type
MCUr
Series
LPCXpressor
Datasheets

Specifications of OM13000

Contents
Board
Svhc
No SVHC (18-Jun-2010)
Mcu Supported Families
LPC1768
Silicon Family Name
LPC17xx
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Ic Product Type
Debugger
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
LPC1768
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-5101

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
OM13000
Manufacturer:
HARRIS
Quantity:
120
Part Number:
OM13000
Manufacturer:
NXP
Quantity:
25
Part Number:
OM13000Ј¬598
Manufacturer:
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Quantity:
27
Document information
Info
Keywords
Abstract
ES_LPC176x
Errata sheet LPC1769/68/67/66/65/64/63
Rev. 8 — 22 March 2011
Content
LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763
errata
This errata sheet describes both the known functional problems and any
deviations from the electrical specifications known at the release date of
this document.
Each deviation is assigned a number and its history is tracked in a table.
Errata sheet

Related parts for OM13000

OM13000 Summary of contents

Page 1

ES_LPC176x Errata sheet LPC1769/68/67/66/65/64/63 Rev. 8 — 22 March 2011 Document information Info Content Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763 errata Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications ...

Page 2

... DD(REG)(3V3) Added RTC.1. Removed Ethernet.1; LPC1765 does not have Ethernet feature. The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added I2S.1 and Ethernet.1 Added MCPWM.1 http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. ...

Page 3

... NXP Semiconductors 1. Product identification The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This Errata Sheet covers the following revisions of the LPC176x: Table 1. ...

Page 4

... NXP Semiconductors Table 3. AC/DC deviations table AC/DC Short description deviations n/a n/a Table 4. Errata notes table Errata notes Short description [1] Note.1 On the LPC176x, for USB operation, the supply voltage ) range must be 3.0 V  DD(3V3) [1] LPC1769/68/66/65/64 only. ES_LPC176X Errata sheet Errata sheet LPC1769/68/67/66/65/64/63 ...

Page 5

... NXP Semiconductors 3. Functional problems detail 3.1 RTC.1: The Real Time Clock (RTC) does not work reliably within the temperature specification Introduction: The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC is clocked by a separate 32 kHz oscillator that produces internal time reference ...

Page 6

... NXP Semiconductors 3.3 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent (LPC1769/68/67/66/64 only) Introduction: The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached ...

Page 7

... NXP Semiconductors 3.4 PLL0.1: PLL0 (Main PLL) remains enabled and connected in Deep Sleep and Power-down modes Introduction: If the main PLL (PLL0) is enabled and connected before entering Deep Sleep or Power-down modes, main PLL (PLL0) automatically turns off and disconnects after the chip enters Deep Sleep mode or Power-down mode leading to reduced power consumption ...

Page 8

... NXP Semiconductors 3.5 PCLKSELx.1: Peripheral Clock Selection Registers must be set before enabling and connecting PLL0 Introduction: A pair of bits in the Peripheral Clock Registers (PCLKSEL0 and PCLKSEL1) controls the rate of the clock signal that will be supplied to APB0 and APB1 peripherals. Problem: If the Peripheral Clock Registers (PCLKSEL0 and PCLKSEL1) are set or changed after PLL0 is enabled and connected, the value written into the Peripheral Clock Selection Registers may not take effect ...

Page 9

... NXP Semiconductors 3.7 V DD(REG)(3V3) temperature range 40  C Introduction: The device has a regulator supply voltage (V 3.6 V for the temperature range 40  C. Problem: The device does not work when the regulator supply voltage (V 3.0 V for temperature range 40  C. ...

Page 10

... NXP Semiconductors 3.8 ADC.1: External sync inputs not operational Introduction: In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options Problem: The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2 ...

Page 11

... NXP Semiconductors 3.9 PWM.1: When updating the duty cycle for PWM1.1 from 100 %, in some cases the output can stay low for a full PWM period before the update takes effect Introduction: On the LPC176x PWM peripheral, two match registers can be used to provide a single edge controlled PWM output ...

Page 12

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 13

... NXP Semiconductors 7. Contents 1 Product identification . . . . . . . . . . . . . . . . . . . . 3 2 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Functional problems detail . . . . . . . . . . . . . . . . 5 3.1 RTC.1: The Real Time Clock (RTC) does not work reliably within the temperature specification . . . 5 Introduction Problem Work-around 3.2 I2S.1: The XY divider (8-bit Fractional Rate Divider) will not work for PCLK_I2S (Peripheral clock for I2S) higher than 74 MHz (LPC1769/68/67/66/65/63 only) ...

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