OM13000 NXP Semiconductors, OM13000 Datasheet - Page 10
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OM13000
Manufacturer Part Number
OM13000
Description
BOARD LPCXPRESSO LPC1768
Manufacturer
NXP Semiconductors
Type
MCUr
Series
LPCXpressor
Specifications of OM13000
Contents
Board
Svhc
No SVHC (18-Jun-2010)
Mcu Supported Families
LPC1768
Silicon Family Name
LPC17xx
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Ic Product Type
Debugger
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
LPC1768
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-5101
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
OM13000
Manufacturer:
HARRIS
Quantity:
120
Company:
Part Number:
OM13000Ј¬598
Manufacturer:
NXP
Quantity:
27
NXP Semiconductors
ES_LPC176X
Errata sheet
Fig 1.
A/D control register options
3.8 ADC.1: External sync inputs not operational
Introduction:
In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by
using the following options in the A/D Control Register:
Problem:
The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably
and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this
problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC
trigger from GPIO) is estimated as follows:
The probability of error is not affected by the frequency of ADC start conversion edges.
Work-around:
In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24
set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion
by connecting an external trigger signal to a capture input pin (CAPx) from a Timer
peripheral to generate an interrupt. The timer interrupt routine can then start the ADC
conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated
from a timer match register.
•
•
•
For PCLK_ADC = 120 MHz, probability error = 12 %
For PCLK_ADC = 50 MHz, probability error = 6 %
For PCLK_ADC = 12 MHz, probability error = 1.5 %
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 22 March 2011
Errata sheet LPC1769/68/67/66/65/64/63
ES_LPC176x
© NXP B.V. 2011. All rights reserved.
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