C8051F350DK Silicon Laboratories Inc, C8051F350DK Datasheet - Page 146

DEV KIT FOR F350/351/352/353

C8051F350DK

Manufacturer Part Number
C8051F350DK
Description
DEV KIT FOR F350/351/352/353
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F350DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350, 351, 352, 353
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1083

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F350DK
Manufacturer:
SiliconL
Quantity:
8
C8051F350/1/2/3
146
Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis-
Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.
R/W
R/W
Bit7
Bit7
ter P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
(Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless
of the value of P0MDOUT).
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
R/W
R/W
Bit6
Bit6
SFR Definition 18.5. P0MDOUT: Port0 Output Mode
SFR Definition 18.6. P0SKIP: Port0 Skip
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.1
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
R/W
R/W
Bit0
Bit0
0xD4
0xA4
00000000
00000000
Reset Value
Reset Value

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