C8051F350DK Silicon Laboratories Inc, C8051F350DK Datasheet - Page 173
![DEV KIT FOR F350/351/352/353](/photos/9/23/92327/c8051f350dk_sml.jpg)
C8051F350DK
Manufacturer Part Number
C8051F350DK
Description
DEV KIT FOR F350/351/352/353
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350, 351, 352, 353
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1083
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F350DK
Manufacturer:
SiliconL
Quantity:
8
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20.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
20.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
SPACE
MARK
BIT TIMES
BIT SAMPLING
START
BIT
Figure 20.3. UART Interconnect Diagram
Figure 20.4. 8-Bit UART Timing Diagram
D0
D1
RS-232
MCU
D2
TX
RX
Rev. 1.1
D3
RS-232
LEVEL
XLTR
OR
D4
RX
RX
TX
TX
C8051Fxxx
D5
C8051Fxxx
C8051F350/1/2/3
D6
D7
STOP
BIT
173
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