AT91CAP9A-STK Atmel, AT91CAP9A-STK Datasheet - Page 23

• Manufacturer Part Number: AT91CAP9A-STK
• Description: KIT STARTER FOR AT91CAP9A
• Manufacturer: Atmel
• Series: CAP™r
• Type: MCUr

Specifications of AT91CAP9A-STK

• Contents: Board, CD
• For Use With/related Products: AT91CAP9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6351B–CAP–27-Jun-08
Requirements
2.4.1.2.4 FPGA Clock
2-16
VCCIO7
The MPIO Bus clock MPIOB24 is connected to the CLK1p clock input pin of the FPGA. An additional
external 12 MHz oscillator generates clock to the CLK14p clock input pin of the FPGA.
Spare clock PLL_OUTp and PLL_OUTn are connected to the EI14 interface.
FPGA clock part electrical connection is shown below.
R212
0R
MPIOB24
R215
1K
NC
MPIOB24
M21
N20
M20
N19
N22
N21
C10
D10
A10
B10
L21
L20
N3
M2
N4
M3
N1
N2
Y4
C9
B9
L2
L3
EP2S15F484
U19K
CLK1p
CLK3p
CLK9p
CLK11p
CLK1n
CLK3n
CLK9n
CLK11n
CLK0p/DIFFIO_RX_C0p
CLK2p/DIFFIO_RX_C1p
CLK8p/DIFFIO_RX_C2p
CLK10p/DIFFIO_RX_C3p
CLK0n/DIFFIO_RX_C0n
CLK2n/DIFFIO_RX_C1n
CLK8n/DIFFIO_RX_C2n
CLK10n/DIFFIO_RX_C3n
PLL_ENA
PLL5_OUT0p
PLL5_OUT1p
PLL5_OUT0n
PLL5_OUT1n
PLL5_FBp/OUT2p
PLL5_FBn/OUT2n
1
2
K3750HBE-12MHz
OE
GND
Y5
R197
10K
PLL6_FBp/OUT2p
PLL6_FBn/OUT2n
VCC
OUT
CLOCK & PLL
PLL6_OUT0p
PLL6_OUT1p
PLL6_OUT0n
PLL6_OUT1n
CLK12p
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
4
3
CLK4p
CLK5p
CLK6p
CLK7p
CLK4n
CLK5n
CLK6n
CLK7n
CLK_12M_R
AB13
AA12
AA11
Y10
B11
B12
A13
C13
AA13
Y12
Y11
W10
C11
C12
B13
D13
AB10
AA9
AA10
Y9
W9
V9
C279
330pF
R204
22R
AT91CAP9-STK Starter Kit User Guide
R220
0R
R221
0R
CLK_12M_FPGA
1
C280
100nF
BLM18PG600
L25
2
FPGA_PLLOUTp
FPGA_PLLOUTn
3V3
C281
100nF