AT91CAP9A-STK Atmel, AT91CAP9A-STK Datasheet - Page 43

• Manufacturer Part Number: AT91CAP9A-STK
• Description: KIT STARTER FOR AT91CAP9A
• Manufacturer: Atmel
• Series: CAP™r
• Type: MCUr

Specifications of AT91CAP9A-STK

• Contents: Board, CD
• For Use With/related Products: AT91CAP9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D
C
B
A
PC[14..19]
VBUS
SHDN
PD4
PC0
PC28
PC2
PC1
PC3
RESET_SOFT_FPGA#
RESET_FPGA#
DONE_FPGA
PC[6..11]
PC[22..27]
MPIOA[0..31]
MPIOB[0..44]
FPGA_IO[0..95]
1V8_CAP9
1V8_FPGA
1V2_CAP9
1V2_USB
1V2_SAVE
1V2_FPGA
1V8_FPGA
VDDMPIO
1V2_FPGA
VCCIO4
VCCIO6
VCCIO7
VCCIO8
3V3
3V3
3V3
5V
5
01 - POW ER SUPPLY
01 - POW ER SUPPLY
LCD & TSC
07 - LCD & TSC
04 - FPGA STRATIX 2
04 - FPGA STRATIX 2
5V
3V3
1V8_CAP9
1V8_FPGA
GND
1V2_CAP9
1V2_USB
1V2_SAVE
1V2_FPGA
VBUS
SHDN
FIQ#
3V3
GND
PCI
VCTRL
R[0..5]
G[0..5]
B[0..5]
DCLK
HSYNC
DTMG
3V3
1V8
VDDMPIO
1V2
VCCIO4
VCCIO6
VCCIO7
VCCIO8
GND
MPIOA[0..31]
MPIOB[0..44]
FPGA_IO[0..95]
RESET_SOFT_FPGA
RESET_FPGA#
CONF_DONE
RESET_SOFT_FPGA#
DONE_FPGA_CAP9
RST_FPGA_CAP9
CHARGER_IRQ
RESET_FPGA#
RESET_CAP9#
PIO_BACKUP
DONE_FPGA
ASDO_CAP9
nCSO_CAP9
DCLK_CAP9
TDO_FPGA
TDO_CAP9
nCE_CAP9
TSC_CS#
TMS_ICE
Pages 3 to 6
Page 19
TCK_ICE
Pages 11 to 13
3V3_ITB
5V_ITB
NTRST
NTRST
TWCK
NRST
SPCK
MOSI
MISO
BUSY
TWD
IRQ
TW CK
TW D
PB10
PA11
PA6
PA7
RESET_FPGA#
PA12
RESET_SOFT_FPGA#
DONE_FPGA
PA13
PA2
PA1
PA0
PA3
PC5
PC4
NTRST
PB3
PB6
PB7
PB8
JTAG_TCK
JTAG_TMS
JTAG_TDO_FPGA
JTAG_TDO_CAP9
NRST
NTRST
RESET_CAP9
4
SHDN
TW D
TW CK
MPIOB24
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..12]
MPIOA[0..31]
MPIOB[0..44]
1V8_CAP9
1V2_CAP9
VDDMPIO
1V2_SAVE
1V2_USB
PA1
PA0
PA4
PA2
RESET_CAP9
PA15
PB2
PB0
PB1
VDDANA
VDDIOP1
VDDIOM
VDDIOP1
3V3
03 - AT91CAP9
03 - AT91CAP9
06 - AUDIO & ANALOG
06 - AUDIO & ANALOG
SDCARD
08 - SDCARD
3V3
1V8
1V2
VDDANA
VDDIOP1
VDDIOM
VDDMPIO
1V2_SAVE
1V2_USB
GND
NRST
NTRST
RESET_CAP9
SHDN
TWD
TWCK
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..12]
MPIOA[0..31]
MPIOB[0..44]
MPIOB24
TCK_ICE
TMS_ICE
TDO_FPGA
TDO_CAP9
MOSI
MISO
AUDIO_CS#
SPCK
RESET#
MCLK
SDIN
LRFS
BCLK
3V3
GND
NANDWE
MCI_CDA
NBS[0..3]
NANDOE
Pages 8 to 10
Pages 17 & 18
MCI_DA0
MCI_DA1
MCI_DA2
MCI_DA3
Page 20
D[16..31]
A[18..25]
SDDRCS
NANDCS
VDDANA
MCI_CK
MCI_CD
D[0..15]
A[0..17]
BA[0..1]
SDCLK
SDCKE
SDA10
SDWE
HSDM
HDMB
HDMA
HSDP
FSDM
HDPB
HDPA
FSDP
ADC1
ADC2
ADC3
ADC4
GND
RAS
CAS
3V3
3
NBS[0..3]
BA[0..1]
VDDANA
3V3
ADC1
ADC2
ADC3
ADC4
NANDCS
NANDW E
NANDOE
HSDM
HSDP
FSDP
FSDM
HDMB
HDPB
HDMA
HDPA
PA16
PA18
PA19
PA20
PA21
PC21
PA17
D[0..15]
D[16..31]
A[0..17]
A[18..25]
D[0..31]
A[2..15]
SDCLK
SDCKE
SDCS
SDRAS
SDCAS
SDW E
SDA10
PA8
VBUS
PC30
PC31
BA0
BA1
NBS0
NBS1
NBS2
NBS3
09 - MEMORY
09 - MEMORY
05 - COMMUNICATION
05 - COMMUNICATION
D[0..31]
A[2..15]
SD_CLK
SD_CKE
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
SDA10
SD_BA0
SD_BA1
SD_DQM0
SD_DQM1
SD_DQM2
SD_DQM3
HSDM
HSDP
FSDP
FSDM
USB_PRES
VBUS
HDMB
HDPB
HDMA
HDPA
DRXD
DTXD
PB17
PB18
1
1
J52
J52
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
J53
J53
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
Rév.
Rév.
Rév.
C02 21/05/08
C02 21/05/08
C02 21/05/08
Date
Date
Date
VDDIO_ETH
3
3
VDD_MEM
NOR_CS#
EPWDN#
ERX[1..0]
FN_R/B#
FN_WP#
FN_WE#
Page 21
ETX[1..0]
ECRSDV
EREFCK
VDD_IO
RESET#
FN_ALE
FN_CLE
FN_CE#
FN_RE#
EMIRQ#
Auteur
Auteur
Auteur
ERXER
ETXEN
ERST#
EMDIO
OBO
OBO
OBO
Pages 14 to 16
EMDC
MOSI
MISO
SPCK
GND
GND
3V3
5V
PB13
ADC1
PB14
ADC2
Création
Création
Création
2, Chemin du Ruisseau BP 121
2, Chemin du Ruisseau BP 121
2, Chemin du Ruisseau BP 121
69136 Ecully
69136 Ecully
69136 Ecully
Tél : [phone]
Tél : [phone]
Tél : [phone]
Fax : [phone]
Fax : [phone]
Fax : [phone]
www.adeneo.adetelgroup.com
www.adeneo.adetelgroup.com
www.adeneo.adetelgroup.com
Historique / Background history
Historique / Background history
Historique / Background history
2
RESET_CAP9
5V
VDDIOM
3V3
3V3
PD11
RESET_CAP9
NANDW E
A21
A22
NANDCS
NANDOE
PA1
PA0
PA5
PA2
PB21
PB31
PB22
PB9
PB11
PB29
PB30
3V3
ERX[1..0]
ETX[1..0]
PB19
PB20
ERX1
ERX0
Format
Format
Format
A3
A3
A3
Projet / Project
Projet / Project
Projet / Project
Schéma électronique / Schematic
Schéma électronique / Schematic
Schéma électronique / Schematic
Date:
Date:
Date:
1
1
CAP9-STK
CAP9-STK
CAP9-STK
TOP LEVEL
TOP LEVEL
TOP LEVEL
J54
J54
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
J55
J55
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
Dessinateur / Drawer
Dessinateur / Drawer
Dessinateur / Drawer
O. Boitet
O. Boitet
O. Boitet
W ednesday, May 21, 2008
W ednesday, May 21, 2008
W ednesday, May 21, 2008
PB26
PB25
PB27
TW CK
TW D
PC29
PA27
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..12]
FPGA_IO[0..95]
1V8_CAP9
3
3
VDDIOP1
VCCIO4
VCCIO6
VCCIO7
VCCIO8
3V3
5V
ETX1
ETX0
PB15
ADC3
PB16
ADC4
02 - IO CONNECTORS & PROTO AREA
02 - IO CONNECTORS & PROTO AREA
Page 7
5V
3V3
1V8_CAP9
VDDIOP1
VCCIO4
VCCIO6
VCCIO7
VCCIO8
GND
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..12]
TWCK
TWD
FPGA_IO[0..95]
PCK0
PCK1
PB24
PB23
PB28
Référence / Reference
Référence / Reference
Référence / Reference
ADEC101389001
ADEC101389001
ADEC101389001
1
Page
Page
Page
2
2
2
de / of
de / of
de / of
21
21
21
C02
C02
C02
Rév.
Rév.
Rév.
D
C
B
A