AT91CAP9A-STK Atmel, AT91CAP9A-STK Datasheet - Page 51

• Manufacturer Part Number: AT91CAP9A-STK
• Description: KIT STARTER FOR AT91CAP9A
• Manufacturer: Atmel
• Series: CAP™r
• Type: MCUr

Specifications of AT91CAP9A-STK

• Contents: Board, CD
• For Use With/related Products: AT91CAP9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D
C
B
A
3V3
GND
1
1
1
1
C107
C107
33pF
33pF
C109
C109
33pF
33pF
C111
C111
22pF
22pF
C114
C114
22pF
22pF
5
2
2
2
2
Y2
Y2
12MHz_20pF
12MHz_20pF
Y3
Y3
32768Hz_12.5pF
32768Hz_12.5pF
3V3
OSC32K_XIN
OSC32K_XOUT
OSC12M_XIN
OSC12M_XOUT
HSDM
FSDM
HSDP
FSDP
HDPA
HDMA
HDPB
HDMB
H20
H19
E19
E20
U6B
U6B
AT91CAP9
AT91CAP9
CPN = AT91ICS039
CPN = AT91ICS039
OSC12M_XIN
OSC12M_XOUT
OSC32K_XIN
OSC32K_XOUT
CAP9 - MISC POWER & ANALOG
CAP9 - MISC POWER & ANALOG
HSDM
FSDM
HSDP
FSDP
4
A20
A18
A19
A17
G16
H16
C16
B16
C17
D17
F15
F14
CAP9 - USB, PLL, ICE
U6I
U6I
AT91CAP9
AT91CAP9
CPN = AT91ICS002
CPN = AT91ICS002
HSDM
UTMI_FSDM
HSDP
UTMI_FSDP
ID
VBUS
VBUS_ON
VBUS_DRV
USBHA_DP
USBHA_DM
USBHB_DP
USBHB_DM
CAP9 - SYSTEM & USB
CAP9 - SYSTEM & USB
NTRST
JTAGSEL
WKUP0
NTRST
SHDW
RTCK
NRST
USBDEV_BIAS
BMS
TMS
TCK
TDO
TST
TDI
LFT_PLL480
LFT_PLLA
LFT_PLLB
C9
C10
D10
B8
E10
B7
F18
H13
A7
F19
G19
A6
VDDBU
JTAGSEL
TST
BMS
D18
F20
G20
C20
LFT_PLL480
LFT_PLLA
LFT_PLLB
VBG
R48
R48
1K
1K
W KUP0
J68
J68
3
J31
J31
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
3
TDO
S6
S6
R51
R51
953R
953R
R54
R54
6K81
6K81
1
TCK_ICE
TMS_ICE
TP16
TP16
R53
R53
1K40
1K40
RESET_CAP9
BP
BP
1
1
3V3
R46
R46
100K
100K
C110
C110
1nF
1nF
C113
C113
1nF
1nF
R49
R49
100K
100K
VDDBU
2
2
1
1
C108
C108
10nF
10nF
C115
C115
10pF
10pF
1
VDDBU
2
2
C112
C112
10nF
10nF
2
R228
R228
10M
10M
NC
NC
SHDN
Rév.
Rév.
Rév.
C02 21/05/08
C02 21/05/08
C02 21/05/08
TDI_ICE
TMS
TCK
RTCK
TDO_CAP9
Date
Date
Date
Auteur
Auteur
Auteur
OBO
OBO
OBO
Création
Création
Création
R38
R38
100K
100K
2, Chemin du Ruisseau BP 121
2, Chemin du Ruisseau BP 121
2, Chemin du Ruisseau BP 121
69136 Ecully
69136 Ecully
69136 Ecully
Tél : [phone]
Tél : [phone]
Tél : [phone]
Fax : [phone]
Fax : [phone]
Fax : [phone]
www.adeneo.adetelgroup.com
www.adeneo.adetelgroup.com
www.adeneo.adetelgroup.com
Historique / Background history
Historique / Background history
Historique / Background history
2
R44
R44
0R
0R
NRST
3V3
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
R42
R42
0R
0R
3
TDO_ICE
R39
R39
100K
100K
NRST
J59
J59
Format
Format
Format
1
A3
A3
A3
Projet / Project
Projet / Project
Projet / Project
Schéma électronique / Schematic
Schéma électronique / Schematic
Schéma électronique / Schematic
Date:
Date:
Date:
CAP9-STK
CAP9-STK
CAP9-STK
SYSTEM USB CLOCK
SYSTEM USB CLOCK
SYSTEM USB CLOCK
R40
R40
100K
100K
0R
0R
R45
R45
TDO
R43
R43
NC
NC
Dessinateur / Drawer
Dessinateur / Drawer
Dessinateur / Drawer
O. Boitet
O. Boitet
O. Boitet
Tuesday, May 20, 2008
Tuesday, May 20, 2008
Tuesday, May 20, 2008
R41
R41
100K
100K
0R
0R
ICE connector
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
3
J60
J60
HE10_2X10PTS_MC
HE10_2X10PTS_MC
Référence / Reference
Référence / Reference
Référence / Reference
ADEC101389001
ADEC101389001
ADEC101389001
1
11
13
15
17
19
1
1
3
5
7
9
J30
J30
TDO_ICE
Page
Page
Page
2
4
6
8
10
12
14
16
18
20
10
10
10
TDO_FPGA
de / of
de / of
de / of
21
21
21
C02
C02
C02
Rév.
Rév.
Rév.
D
C
B
A