C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 101

• Manufacturer Part Number: C8051F020-TB
• Description: BOARD PROTOTYPING W/C8051F020
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020-TB

• Contents: Board
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F020
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™
instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has
a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see descrip-
tion in
RAM, 128 byte Special Function Register (SFR) address space (see
description in
interfaces directly with the MCUs' analog and digital subsystems providing a complete data acquisition or control-
system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes
the following features:
-
-
-
-
-
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
8/4 Byte-Wide I/O Ports
Section
CIP-51 MICROCONTROLLER
Section
22), two full-duplex UARTs (see description in
17). The CIP-51 also includes on-chip debug hardware (see description in
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
Figure 12.1. CIP-51 Block Diagram
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
TMP2
DATA BUS
DATA BUS
D8
D8
D8
Rev. 1.4
-
-
-
-
-
A16
D8
D8
D8
D8
B REGISTER
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
Section 20
REGISTER
INTERRUPT
Section
ADDRESS
INTERFACE
INTERFACE
INTERFACE
MEMORY
SRAM
SFR
BUS
12.2.6), and 8/4 byte-wide I/O Ports (see
and
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
C8051F020/1/2/3
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
Section
SYSTEM_IRQs
21), 256 bytes of internal
Section
24), and
101