C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 181

• Manufacturer Part Number: C8051F020-TB
• Description: BOARD PROTOTYPING W/C8051F020
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020-TB

• Contents: Board
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F020
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bits7-0:
Note:
Bits7-0:
Note:
P6.7
P7.7
R/W
R/W
Bit7
Bit7
P6.[7:0]: Port6 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P6.n pin is logic low.
1: P6.n pin is logic high.
P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See
ORY INTERFACE AND ON-CHIP XRAM” on page 145
Memory Interface.
P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or
as D[7:0] in Non-multiplexed mode). See
FACE AND ON-CHIP XRAM” on page 145
Interface.
P6.6
P7.6
R/W
R/W
Bit6
Bit6
P6.5
P7.5
R/W
R/W
Bit5
Bit5
Figure 17.23. P6: Port6 Data Register
Figure 17.24. P7: Port7 Data Register
P6.4
P7.4
R/W
R/W
Bit4
Bit4
P6.3
P7.3
Section “16. EXTERNAL DATA MEMORY INTER-
R/W
R/W
Bit3
Bit3
Rev. 1.4
for more information about the External Memory
P6.2
P7.2
R/W
R/W
Bit2
Bit2
Section “16. EXTERNAL DATA MEM-
for more information about the External
P6.1
P7.1
C8051F020/1/2/3
R/W
R/W
Bit1
Bit1
P6.0
P7.0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
Reset Value
11111111
Reset Value
11111111
0x86
0x96
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