C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 214

BOARD PROTOTYPING W/C8051F020

C8051F020-TB

Manufacturer Part Number
C8051F020-TB
Description
BOARD PROTOTYPING W/C8051F020
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F020-TB

Contents
Board
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F020
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F020/1/2/3
214
Bits7-0:
Bits7-0:
Bits7-0:
R/W
R/W
R/W
Bit7
Bit7
Bit7
SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When data is
written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a
byte to SBUF0 is what initiates the transmission. A read of SBUF0 returns the contents of the receive
latch.
SADDR0.[7:0]: UART0 Slave Address
The contents of this register are used to define the UART0 slave address. Register SADEN0 is a bit
mask to determine which bits of SADDR0 are checked against a received address: corresponding bits
set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0 are “don’t cares”.
SADEN0.[7:0]: UART0 Slave Address Enable
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0 slave
address.
0: Corresponding bit in SADDR0 is a “don’t care”.
1: Corresponding bit in SADDR0 is checked against a received address.
Figure 20.11. SADEN0: UART0 Slave Address Enable Register
R/W
R/W
R/W
Bit6
Bit6
Bit6
Figure 20.10. SADDR0: UART0 Slave Address Register
Figure 20.9. SBUF0: UART0 Data Buffer Register
R/W
R/W
R/W
Bit5
Bit5
Bit5
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.4
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
00000000
00000000
Reset Value
Reset Value
Reset Value
0xA9
0xB9
0x99

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