C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 173

• Manufacturer Part Number: C8051F020-TB
• Description: BOARD PROTOTYPING W/C8051F020
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020-TB

• Contents: Board
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F020
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bits7-0:
Bits7-0:
Note:
P0.7
R/W
R/W
Bit7
Bit7
P0.[7:0]: Port0 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P0MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Note: P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory Interface.
See
page 145
for External Memory accesses.
P0MDOUT.[7:0]: Port0 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on
P0.6
R/W
R/W
Bit6
Bit6
Figure 17.11. P0MDOUT: Port0 Output Mode Register
for more information. See also Figure 17.9 for information about configuring the Crossbar
P0.5
R/W
R/W
Bit5
Bit5
Figure 17.10. P0: Port0 Data Register
P0.4
R/W
R/W
Bit4
Bit4
P0.3
R/W
R/W
Bit3
Bit3
Rev. 1.4
P0.2
R/W
R/W
Bit2
Bit2
P0.1
C8051F020/1/2/3
R/W
R/W
Bit1
Bit1
(bit addressable)
P0.0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
00000000
Reset Value
11111111
Reset Value
0xA4
0x80
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