C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 134
![BOARD PROTOTYPING W/C8051F060](/photos/28/94/289414/tqfp-100_sml.jpg)
C8051F060-TB
Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F060-TB
Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F060/1/2/3/4/5/6/7
13.2.6.3.SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts.
In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the
CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR
Page 0x0F). The device is also using the Programmable Counter Array (PCA) and the 10-bit ADC (ADC2)
window comparator to monitor a voltage. The PCA is timing a critical control function in its interrupt service
routine (ISR), so its interrupt is enabled and is set to high priority. The ADC2 is monitoring a voltage that is
less important, but to minimize the software overhead its window comparator is being used with an associ-
ated ISR that is set to low priority. At this point, the SFR page is set to access the Port 5 SFR (SFRPAGE =
0x0F). See Figure 13.4 below.
Figure 13.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5
SFR Page
Stack SFR's
0x0F
SFRPAGE
(Port 5)
SFRNEXT
SFRLAST
134
Rev. 1.2
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