C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 216

BOARD PROTOTYPING W/C8051F060

C8051F060-TB

Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F060-TB

Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F060/1/2/3/4/5/6/7
216
Bits7-0:
Note:
Bits7-0:
P2.7
R/W
R/W
Bit7
Bit7
P1MDOUT.[7:0]: Port1 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
P2.[7:0]: Port2 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.
P2.6
R/W
R/W
Bit6
Bit6
Figure 18.13. P1MDOUT: Port1 Output Mode Register
P2.5
R/W
R/W
Bit5
Bit5
Figure 18.14. P2: Port2 Data Register
P2.4
R/W
R/W
Bit4
Bit4
Rev. 1.2
P2.3
R/W
R/W
Bit3
Bit3
P2.2
R/W
R/W
Bit2
Bit2
P2.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P2.0
R/W
R/W
Bit0
Bit0
0xA5
F
0xA0
All Pages
Addressable
Reset Value
Reset Value
00000000
11111111
Bit

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