C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 245
C8051F060-TB
Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F060-TB
Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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20.4.3. Data Register
The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just
been received. Software can read or write to this register while the SI flag is set to logic 1; software should
not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag reads logic 0
since the hardware may be in the process of shifting a byte of data in or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. Therefore, SMB0DAT always contains the last data byte present on the bus. In the event
of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in
SMB0DAT.
20.4.4. Address Register
The SMB0ADR Address register holds the slave address for the SMBus0 interface. In slave mode, the
seven most-significant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the
recognition of the general call address (0x00). If Bit0 is set to logic 1, the general call address will be recog-
Bits7-0:
R/W
Bit7
SMB0DAT: SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial inter-
face or a byte that has just been received on the SMBus0 serial interface. The CPU can
read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set to
logic 1. When the SI flag is not set, the system may be in the process of shifting data and the
CPU should not attempt to access this register.
R/W
Bit6
Figure 20.10. SMB0DAT: SMBus0 Data Register
R/W
Bit5
R/W
Bit4
Rev. 1.2
R/W
Bit3
C8051F060/1/2/3/4/5/6/7
R/W
Bit2
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xC2
0
Reset Value
00000000
245
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