MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 51

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
The PCI configuration registers which are set at hard reset sequence are shown in Figure 5-1
5.1.4
Soft reset may be generated on the board from the following sources:
CS10PC
ALD_EN
PCI_MODCK
MODCK_HI
Applies only ONCE after power-up reset.
• COP/JTAG port
• Manual soft reset
Field
1
Soft Reset
Table 5-2. E
Reserved
24:25
28:31
Data
Bus
Bits
Class Code
BIST Control
26
27
MAX LAT
PCI Arbiter Control
Subsystem ID
Figure 5-1. PCI Host Configuration Registers
Device ID (0x18C0)
2
Value
‘1010’
Prog
[Bin]
PROM Hard Reset Configuration Word (continued)
’01’
PCI Status
’0’
’1’
PIMMR Base Address Register
Subclass Code
Header Type
CS10~/BCTL1/DBG_DIS~ functions as BCTL1
PCI Auto Load Enable. When high, PCI Bridge
Configuration is done automatically from the
FLASH/E
- PPC core should be disabled) right after the
Hard Configuration Word. When low, the PPC
Core should configure the PCI Bridge.
Determines PCI clock settings as set by
PCI_MODCKH:
‘0’ - PCI clock set by PCI_MODCKH
‘1’ - PCI clock is divided according to
PCI_MODCKH
Determines the Core’s frequency out of
power-up reset.
MIN GNT
Chapter 5. Module Design
Capability Pointer
2
PROM (CPM is configuration source
/ / / / / / / /
/ / / / / / / /
Standard Programming
Implication
Latency Timer
Interrupt Pin
Subsystem Vendor ID
PCI Function
Vendor ID (0x1057)
PCI Command
Cache Line Size
Interrupt Line
Reset and Reset Configuration
Revision ID
Offset In
Offset (Hex)
Flash
[Hex]
Address
18
00
04
08
0C
10
14
18
2C
34
3C
38
40
44
Value
[Hex]
5A