MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 54

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset and Reset Configuration
A simple generic interrupt controller is implemented using a CPLD device. The interrupt
controller is implemented as an interrupt register and an interrupt mask register. The
interrupt controller has its’ own dedicated chip-select line (CS3). A simple priority scheme
is devised to prioritize the interrupts from different slots. The PCI IRQ routing are
according to Figure 5-2.
An interrupt request in any of the INTx lines, sets 3 interrupt bits in the PCI interrupt
register (if not masked in the interrupt mask register) because every INTx line has three
possible interrupt sources. It is up to the user to implement a polling process to verify the
real interrupt source (by polling the interrupt pending bit in the PCI device) and clear the
other two. The PCI interrupt register can be read at any time and accessed at offset 0x0 from
CS3 base address. The description of the PCI interrupt register is in Table 5-3.
BI
T
0
1
2
3
PowerQUICC II
MNEMONIC
PCI0_INTC
PCI0_INTD
PCI0_INTA
PCI0_INTB
IRQ2
CONTROL
ADDRESS
Table 5-3. PCI Interrupt Register Description
PCI Slot 0 INTA. PCI Slot 0 Interrupt A:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
PCI Slot 0 INTB. PCI Slot 0 Interrupt B:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
PCI Slot 0 INTC. PCI Slot 0 Interrupt C:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
PCI Slot 0 INTD. PCI Slot 0 Interrupt D:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
DATA
Figure 5-2. PCI Interrupt Routing Scheme
IRQ
Controller
MPC8272ADS User Guide
Interrupt
PCI
Function
INTA
INTC
INTB
INTD
SLOT
A
C
0
B
D
SLOT
1
A
C
B
D
SLOT
PON
DEF
2
A
C
0
0
0
0
B
D
A
T.
T
R
R
R
R