MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 58

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bus Configuration
5.3
The MPC8272on the board is configured in one possible bus mode, which is single
MPC8272 mode.
5.3.1
The MPC8272 is configured in single MPC8272 mode, assuming only one MPC8272 on
the 60x bus with no support for external master access. This configuration allows for
internal address multiplexing to occur, which makes external address multiplexers
redundant and unused, improving SDRAM performance.
5.4
To achieve optimal performance, it is necessary to reduce the capacitive load over the 60X
bus as much as possible. The slower devices on the bus, that is, the Flash SIMM, E
ATM UNI M/P interface, PCI interrupt controller and the BCSR are buffered, while the
SDRAM is not buffered from the 60X bus.
Latches are provided over address and strobe (when necessary) lines while transceivers are
provided for data. Use is done with 74ALVT buffers (by Philips) which are 3.3 V operated
and 5-V tolerant
MPC8272 requires). This type of buffer reduces noise on board due to reduced transition
amplitude.
To reduce noise and reflections further, serial damping resistors are placed over SDRAM
address and all MPC8272 strobe lines.
The data transceivers are open only if there is an access to a valid
or during hard reset configuration
1
2
3
Required for Flash, E
An address which is covered in a Chip-Select region, that controls a buffered device.
To allow a configuration word stored in the Flash/E
Buffering
Bus Configuration
Single PowerQUICC II Mode
CLOCK GEN.
1
100 MHZ
, and provide bus hold to reduce pull-up/pull-down resistors count (as the
2
PROM, Interrupt Controller and BCSR
Figure 5-4. PCI Clock Generator Scheme
CLKIN1
MPC8272
MPC8272ADS User Guide
DLLOUT
CLKIN2
3
. Data conflicts are avoided in case an unbuffered
2
PROM memory to become active.
Low Skew Clock Buffer
OUT4
IN
OUT2
OUT3
OUT1
PCI Device
PCI Device
PCI Device
2
#1
#2
#3
buffered board address
2
PROM,