MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 89

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PSRT
PSDMR
MPTPR
Table 6-7. Memory Controller Initialization For 100MHz—E
Reg.
OR4
OR5
OR3
Reg.
BR4
BR5
BR3
SM73228XG1JHBG0 by
Smart Modular Tech.
SM73248XG2JHBG0 by
Smart Modular Tech.
ASM73288XG4JHBG0
by Smart Modular Tech.
SM73228XG1JHBG0 by
Smart Modular Tech.
SM73248XG2JHBG0 by
Smart Modular Tech.
SM73288XG4JHBG0 by
Smart Modular Tech.
PM5384 - ATM UNI
PCI Interrupt Controller
MT48LC8M16A2
(64 MByte)
PPC
Supported
All SDRAMs on board
Device Type
Device Type
Table 6-8. Memory Controller Initialization For 100MHz
Bus
SDRAM
PPC
Single
PowerQ
UICC II
Bus
Mode
PPC
PPC
PPC
Bus
Bus
PPC
Chapter 6. Memory Map
C34F36A3
FFFF8E56
C3801801
C3001801
C2001801
FE000876
FFFF8010
FF800876
FF000876
Init Value
04600801
04731801
Init Value
[hex]
[hex]
2800
13
Base at C3000000, 32 bit port size, no parity,
Base at C2000000, 32 bit port size, no parity,
8MByte block size, CS early negate, 11 w.s.,
16MByte block size, CS early negate, 11 w.s.,
32MByte block size, CS early negate, 11 w.s.,
Divide MPTPR output by 20 (PSRT +1) Generates
Divide Bus clock by 41 (MPTPR+1) (decimal)
Base at C3800000, 32 bit port size, no parity,
GPCM
GPCM
GPCM
Timing relax
Timing relax
Timing relax
Base at 04600000, 8 bit port size, no parity, GPCM
on PPC bus.
32K Byte block size, delayed CS assertion, early
CS and WE negation for write cycle, relaxed
timing, 7 w.s. for read, 8 for write, extended hold
time after read.
Base at 04730000, 32 bit port size, no parity,
GPCM on PPC bus.
32 KByte block size, all types access, 1 w.s.
Page Based Interleaving, Refresh enabled, normal
operation mode, address muxing mode 3, A14-A16 on
BNKSEL, A7 on PSDA10, 8 clocks refresh recovery, 3
clocks precharge to activate delay, 3 clocks activate to
read/write delay, 4 beat burst length, 2 clock last data
out to precharge, 2 clock write recovery time, no extra
cycle on address phase, normal timing for control lines,
3 clocks CAS latency.
refresh every 8.2 µsec., while 15.6µsec. required. This
will work also for 66MHz bus (12.4µsec).
PowerQUICC II Register Programming
2
PROM as Boot Device
Description
Description