MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 87

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
6.2.2
The memory controller on the MPC8272ADS is initialized to 100MHz operation, that is,
the registers’ programming is based on 100-MHz timing calculation. It also works for
slower bus speeds, but the timing must be optimized). The two possible initialization for
the memory controller are the following:
Both options are shown in Table 6-6 and Table 6-7, respectively.
Reg.
OR0
RMR
IMMR
SYPCR
BCR
BR0
Programmed into the E
Register
Table 6-6. Memory Controller Initialization For 100MHz—Flash as Boot Device
• Flash SIMM is assigned to CS0 and E
• Flash SIMM is assigned to CS4 and E
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Memory Controller Register Programming
0001
04700000
FFFFFFC3
100C0000
Device Type
Value[hex]
Init
2
PROM in addresses 0x0, 0x8, 0x10 & 0x18
Table 6-5. SIU Register Programming
Check-Stop Reset enabled.
Internal space @ 0x047000000
Software watchdog timer count - FFFF, Bus-monitor timing FF, PPC Bus-monitor -
Enabled, Local Bus-monitor - Enabled, S/W watch-dog - disabled, S/W watch-dog
(if enabled) causes reset, S/W watch-dog (if enabled) - prescaled.
Single PowerQUICC II, 1 wait-states on address tenure, No L2Cache, 1 clock hit
delay (when L2cache available), 1-level Pipeline depth, Extended transfer mode
enabled for PCC, Extended transfer mode disabled for Local Buses, Odd parity for
PPC & Local Buses, External Master delay enabled, Internal space responds as 64
bit slave for external master (not relevant for this application).
PPC
Bus
Chapter 6. Memory Map
FE001801
FE000876
FF801801
FF001801
FF800876
FF000876
Init Value
[hex]
2
2
PROM is assigned to CS4.
PROM is assigned to CS0.
Base at FF000000, 32 bit port size, no parity,
Base at FE000000, 32 bit port size, no parity,
16MByte block size, CS early negate, 11 w.s.,
32MByte block size, CS early negate, 11 w.s.,
Base at FF800000, 32 bit port size, no parity,
GPCM
GPCM
GPCM
8MByte block size, CS early negate, 11 w.s.,
Timing relax
Timing relax
Timing relax
Description
PowerQUICC II Register Programming
Description