ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 26

• Manufacturer Part Number: ATAVRONEKIT
• Description: KIT AVR/AVR32 DEBUGGER/PROGRMMR
• Manufacturer: Atmel
• Series: AVR®r
• Type: Debuggerr

Specifications of ATAVRONEKIT

• Contents: Programmer/Debugger
• Processor To Be Evaluated: AVR32
• Data Bus Width: 32 bit
• Interface Type: ISP, JTAG
• Core Architecture: AVR
• Kit Contents: ATAVRONEKIT
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Mcu Supported Families: AVR32 32-bit MCU
• For Use With/related Products: AVR® Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13-1.
8067M–AVR–09/10
Program Address
(Base Address)
0x0AE
0x0BC
0x0EC
0x0EE
0x04E
0x05A
0x05E
0x06A
0x07A
0x08E
0x09A
0x0A6
0x0B0
0x0B6
0x0C0
0x0C4
0x0C8
0x0D0
0x0D4
0x0D8
0x0E4
0x040
0x044
0x048
0x056
0x072
0x074
0x080
0x084
0x088
0x096
0x0F4
Reset and Interrupt Vectors (Continued)
Source
NVM_INT_base
PORTB_INT_base
ACB_INT_base
ADCB_INT_base
PORTE_INT_base
TWIE_INT_base
TCE0_INT_base
TCE1_INT_base
SPIE_INT_vect
USARTE0_INT_base
USARTE1_INT_base
PORTD_INT_base
PORTA_INT_base
ACA_INT_base
ADCA_INT_base
TWID_INT_base
TCD0_INT_base
TCD1_INT_base
SPID_INT_vector
USARTD0_INT_base
USARTD1_INT_base
PORTQ_INT_base
PORTH_INT_base
PORTJ_INT_base
PORTK_INT_base
PORTF_INT_base
TWIF_INT_base
TCF0_INT_base
TCF1_INT_base
SPIF_INT_vector
USARTF0_INT_base
USARTF1_INT_base
Interrupt Description
Non-Volatile Memory Interrupt base
Port B Interrupt base
Analog Comparator on Port B Interrupt base
Analog to Digital Converter on Port B Interrupt base
Port E Interrupt base
Two-Wire Interface on Port E Interrupt base
Timer/Counter 0 on port E Interrupt base
Timer/Counter 1 on port E Interrupt base
SPI on port E Interrupt vector
USART 0 on port E Interrupt base
USART 1 on port E Interrupt base
Port D Interrupt base
Port A Interrupt base
Analog Comparator on Port A Interrupt base
Analog to Digital Converter on Port A Interrupt base
Two-Wire Interface on Port D Interrupt base
Timer/Counter 0 on port D Interrupt base
Timer/Counter 1 on port D Interrupt base
SPI on port D Interrupt vector
USART 0 on port D Interrupt base
USART 1 on port D Interrupt base
Port Q INT base
Port H INT base
Port J INT base
Port K INT base
Port F INT base
Two-Wire Interface on Port F INT base
Timer/Counter 0 on port F Interrupt base
Timer/Counter 1 on port F Interrupt base
SPI ion port F Interrupt base
USART 0 on port F Interrupt base
USART 1 on port F Interrupt base
XMEGA A1
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