ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 8

• Manufacturer Part Number: ATAVRONEKIT
• Description: KIT AVR/AVR32 DEBUGGER/PROGRMMR
• Manufacturer: Atmel
• Series: AVR®r
• Type: Debuggerr

Specifications of ATAVRONEKIT

• Contents: Programmer/Debugger
• Processor To Be Evaluated: AVR32
• Data Bus Width: 32 bit
• Interface Type: ISP, JTAG
• Core Architecture: AVR
• Kit Contents: ATAVRONEKIT
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Mcu Supported Families: AVR32 32-bit MCU
• For Use With/related Products: AVR® Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. AVR CPU
6.1
6.2
8067M–AVR–09/10
Features
Overview
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The XMEGA A1 uses the 8/16-bit AVR CPU. The main function of the CPU is program execu-
tion. The CPU must therefore be able to access memories, perform calculations and control
peripherals. Interrupt handling is described in a separate section.
the CPU block diagram.
Figure 6-1.
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This
8/16-bit high performance AVR RISC Architecture
32x8-bit registers directly connected to the ALU
Stack in SRAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M Bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
– 138 instructions
– Hardware multiplier
Peripheral
Module 1
CPU block diagram
CONTROL
STATUS/
Program
Counter
OCD
Peripheral
Module 2
Instruction
Instruction
Program
Register
Memory
Decode
Flash
DATA BUS
SRAM
DATA BUS
ALU
EEPROM
32 x 8 General
Registers
Multiplier/
Purpose
DES
Figure 6-1 on page 8
PMIC
XMEGA A1
shows
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