ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 94

• Manufacturer Part Number: ATAVRONEKIT
• Description: KIT AVR/AVR32 DEBUGGER/PROGRMMR
• Manufacturer: Atmel
• Series: AVR®r
• Type: Debuggerr

Specifications of ATAVRONEKIT

• Contents: Programmer/Debugger
• Processor To Be Evaluated: AVR32
• Data Bus Width: 32 bit
• Interface Type: ISP, JTAG
• Core Architecture: AVR
• Kit Contents: ATAVRONEKIT
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Mcu Supported Families: AVR32 32-bit MCU
• For Use With/related Products: AVR® Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8067M–AVR–09/10
16. DAC has up to ±10 LSB noise in Sampled Mode
17. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
18. DAC has up to ±10 LSB noise in Sampled Mode
19. Conversion lost on DAC channel B in event triggered mode
20. Both DFLLs and both oscillators have to be enabled for one to work
21. Access error when multiple bus masters are accessing SDRAM
The DAC has noise of up to ±10 LSB in Sampled Mode for entire operation range.
Problem fix/Workaround
Use the DAC in continuous mode.
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– ±10 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1
conversions are occasionally lost. This means that not all data-values written to the
Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-
eral clock frequency so the conversion internal never is shorter than 1.5 µs.
In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscil-
lators, the DFLL for both oscillators and both oscillators have to be enabled for one to work.
Problem fix/Workaround
Enable both DFLLs and both oscillators when using automatic runtime calibration for either
of the internal oscillators.
If one bus master (CPU and DMA channels) is using the EBI to access an SDRAM in burst
mode and another bus master is accessing the same row number in a different BANK of the
SDRAM in the cycle directly after the burst access is complete, the access for the second
bus master will fail.
Problem fix/Workaround
Do not put stack pointer in SDRAM and use DMA Controller in 1 byte burst mode if CPU and
DMA Controller are required to access SDRAM at the same time.
XMEGA A1
94