ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 62

• Manufacturer Part Number: ATAVRONEKIT
• Description: KIT AVR/AVR32 DEBUGGER/PROGRMMR
• Manufacturer: Atmel
• Series: AVR®r
• Type: Debuggerr

Specifications of ATAVRONEKIT

• Contents: Programmer/Debugger
• Processor To Be Evaluated: AVR32
• Data Bus Width: 32 bit
• Interface Type: ISP, JTAG
• Core Architecture: AVR
• Kit Contents: ATAVRONEKIT
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Mcu Supported Families: AVR32 32-bit MCU
• For Use With/related Products: AVR® Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8067M–AVR–09/10
Mnemonics
LD
LDD
LD
LD
LD
LDD
STS
ST
ST
ST
ST
ST
ST
STD
ST
ST
ST
STD
LPM
LPM
LPM
ELPM
ELPM
ELPM
SPM
SPM
IN
OUT
PUSH
POP
LSL
LSR
Operands
Rd, -Y
Rd, Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
k, Rr
X, Rr
X+, Rr
-X, Rr
Y, Rr
Y+, Rr
-Y, Rr
Y+q, Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q,Rr
Rd, Z
Rd, Z+
Rd, Z
Rd, Z+
Z+
Rd, A
A, Rr
Rr
Rd
Rd
Rd
Description
Load Indirect and Pre-Decrement
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Load Program Memory
Load Program Memory and Post-Increment
Extended Load Program Memory
Extended Load Program Memory
Extended Load Program Memory and Post-
Increment
Store Program Memory
Store Program Memory and Post-Increment
by 2
In From I/O Location
Out To I/O Location
Push Register on Stack
Pop Register from Stack
Logical Shift Left
Logical Shift Right
Bit and Bit-test Instructions
(RAMPZ:Z)
(RAMPZ:Z)
Rd(n+1)
STACK
(Y + q)
(Z + q)
I/O(A)
Rd(0)
Rd(n)
Rd(7)
Operation
(X)
(X)
(X)
(Y)
(Y)
(Y)
Rd
Rd
Rd
Rd
Rd
Rd
(Z)
(Z)
R0
Rd
Rd
R0
Rd
Rd
Rd
Rd
(k)
C
C
Y
Z
Z
X
X
Y
Y
Z
Z
Z
Z
Z
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Y - 1
(Y)
(Y + q)
(Z)
(Z),
Z+1
Z - 1,
(Z)
(Z + q)
Rd
Rr
Rr,
X + 1
X - 1,
Rr
Rr
Rr,
Y + 1
Y - 1,
Rr
Rr
Rr
Rr
Z + 1
Z - 1
Rr
(Z)
(Z)
(Z),
Z + 1
(RAMPZ:Z)
(RAMPZ:Z)
(RAMPZ:Z),
Z + 1
R1:R0
R1:R0,
Z + 2
I/O(A)
Rr
Rr
STACK
Rd(n),
0,
Rd(7)
Rd(n+1),
0,
Rd(0)
XMEGA A1
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V,H
Z,C,N,V
#Clocks
2
2
1
1
2
2
2
1
1
2
1
1
2
2
1
1
2
2
1
2
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
3
3
3
3
3
3
1
1
1
1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
-
-
(1)
(1)
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