EVAL-ADUC814QS Analog Devices Inc, EVAL-ADUC814QS Datasheet - Page 37

• Manufacturer Part Number: EVAL-ADUC814QS
• Description: KIT DEV FOR ADUC814 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: 8052-corer

Specifications of EVAL-ADUC814QS

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC814
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ON-CHIP PLL
The ADuC814 is intended for use with a 32.768 kHz watch
crystal. An on-board PLL locks onto a multiple (512) of this
32.768kHz frequency to provide a stable 16.777216 MHz clock
for the system. The core can operate at this frequency or at
binary submultiples of it to allow power saving in cases where
maximum core performance is not required. The default core
clock is the PLL clock divided by 8 (2
The PLL is controlled via the PLLCON special function register.
Table 13. PLLCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
OSC_PD
Name
OSC_PD
LOCK
---
---
FINT
CD2
CD1
CD0
LOCK
Description
Oscillator Power-Down Bit.
Set by the user to halt the 32 kHz oscillator in power-down mode.
Cleared by the user to enable the 32 kHz oscillator in power-down mode. This feature allows the oscillator to
continue clocking the TIC even in power-down mode.
PLL Lock Bit. This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external
crystal becomes subsequently disconnected, the PLL rails and the core halts.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due
to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output is 16.78 MHz ± 20%.
Reserved. Should be written with 0.
Reserved. Should be written with 0.
Fast Interrupt Response Bit.
Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency, regardless
of the configuration of the CD2–CD0 bits (see below). Once user code has returned from an interrupt, the core
resumes code execution at the core clock selected by the CD2–CD0 bits.
Cleared by the user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits.
This number determines the frequency at which the microcontroller core operates.
CD2
0
0
0
0
1
1
1
1
CD1
0
0
1
1
0
0
1
1
CD
= 2
---
CD0
0
1
0
1
0
1
0
1
3
) or 2.097152 MHz.
Core Clock Frequency (MHz)
16.777216
8.388608
4.194304
2.097152 (Default Core Clock Frequency)
1.048576
0.524288
0.262144
0.131072
---
Rev. A | Page 37 of 72
PLLCON
SFR Address
Power-On Default
Bit Addressable
FINT
CD2
PLL Control Register
D7H
03H
No
CD1
ADuC814
CD0