HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 15

• Manufacturer Part Number: HS7750KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7. Interrupt
8. Memory Access during User Program Break
9. Cache Operation during User Program Break
10. Loading Sessions
When a one-byte memory is read from the command-line window, the stopping time will be
about 45 ms.
When the NMIB bit in the ICR register is 1, the NMI interrupt is accepted during break and the
program is executed from the NMI interrupt vector. If the program cannot return normally
from the NMI interrupt routine or the value in the general-purpose register is not guaranteed, a
communication timeout error will occur.
The emulator can download the program for the flash memory area (refer to section 6.22,
Download Function to the Flash Memory Area, in the Debugger Part of the SuperH
E10A Emulator User’s Manual). Other memory write operations are enabled for the RAM
area. Therefore, an operation such as memory write or BREAKPOINT should be set only for
the RAM area.
When the memory area can be written by the MMU, do not perform memory write,
BREAKPOINT break, or downloading.
When cache is enabled, the emulator accesses the memory by the following methods:
Therefore, when memory read or write is performed during user program break, the cache state
will be changed.
Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading
sessions. Thus the TCK value will be as follows:
At memory write: Writes through the cache, then writes to the memory.
At memory read: Does not change the cache write mode that has been set.
When HS7750KCI01H is used: TCK = 4.125 MHz
When HS7750KCM01H is used: TCK = 3.75 MHz
TM
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