HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 32

• Manufacturer Part Number: HS7750KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes: 1. The counter for performance measurement has 48 bits. A maximum of 2
2. Displaying the measured result
Note: If a performance counter overflows as a result of measurement, “********” will be
24
When the ratio of the CPU clock to the bus clock is changed in the user program, it is
recommended to select method 2, above, to count the number of cycles.
The following shows examples to measure the performance of the user program by the
performance measurement function.
(i) Measuring cache hit ratio
(ii) Measuring ratio of execution time in specified program area to total execution time
The measured result is displayed in the [Performance Analysis] window or the
PERFORMANCE_ANALYSIS command with hexadecimal (32 bits).
T = C x B / 24
Specify measurement channel 1 to count the cache misses (for data read and write) and
specify measurement channel 2 to count operand accesses (read and write) to the cacheable
area while the cache is enabled. Specify, with both the channels, the measurement from the
start to the end of user program execution.
With the above command settings, the cache miss count and the access count to the
cacheable area can be measured, and the cache hit ratio in the executed user program can
be obtained.
Specify measurement channel 1 to measure the elapsed cycle count from the start to the
end of user program execution. Specify measurement channel 2 to measure the elapsed
cycle count during execution from the specified start PC to the specified
end PC.
With both the channels, the total elapsed cycle and the elapsed cycle for the specified
program area can be measured, and the ratio of the execution time in the specified program
area to the total execution time can be obtained.
2.
3.
4.
5.
displayed.
counts and 16.3-day cycles (when the CPU operating frequency is 200 MHz) can be
measured. If a counter overflow occurs, the count becomes invalid.
When performance measurement conditions are set, canceled, or initialized, the
settings in the UBC are not guaranteed.
Set the same start and end PC values for both channels 1 and 2. If different PC values
are set, the last settings become valid.
When the start and end PC values are set with this command, the value that has been
previously set for UBC becomes invalid.
For details on command-line syntax, refer to the online help.
(T: Execution time; B: Time of one bus clock cycle; C: Count)
48
= 2.8 x 10
14