DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 124
DS-FND-BSX-PC
Manufacturer Part Number
DS-FND-BSX-PC
Description
FOUNDATION BASE SYS W/SYN EXPRES
Manufacturer
Xilinx Inc
Type
Foundation Systemr
Datasheet
1.DS-FND-BSX-PC.pdf
(330 pages)
Specifications of DS-FND-BSX-PC
For Use With/related Products
Xilinx Programmable Logic Devices
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1185
- Current page: 124 of 330
- Download datasheet (3Mb)
Foundation Series 2.1i User Guide
5-22
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9.
From the Design Wizard - Language window, choose VHDL or
Verilog and select Next.
In the Design Wizard - Name window, enter a name for your
macro. Select Next.
Define your ports in the Design Wizard-Ports window. Select
Next.
In the Design Wizards - Machines window, select the number of
state machines that you want. Click Finish. The Wizard creates
the ports and gives you a template in which you can enter your
macro design.
Complete the design for your FSM in the State Editor.
Add the macro to the project by selecting Project
Project from the Project Manager.
You will see the FSM module listed in the Files tab of the Project
Manager.
Following is an example of VHDL code (my_fsm.vhd) generated
from the State Editor for a state machine macro.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity my_fsm is
end;
architecture my_fsm_arch of my_fsm is
-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (S1, S2, S3);
signal Sreg0: Sreg0_type;
port (clk: in STD_LOGIC;
in_a: in STD_LOGIC;
in_b: in STD_LOGIC;
in_c: in STD_LOGIC;
reset: in STD_LOGIC;
out_a: out STD_LOGIC;
out_b: out STD_LOGIC;
out_c: out STD_LOGIC);
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