DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 234

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
11-28
Translation Report
Map Report (FPGAs)
Place and Route Report (FPGAs)
The translation report (.bld) contains warning and error messages
from the three translation processes: conversion of the EDIF or XNF
style netlist to the Xilinx NGD netlist format, timing specification
checks, and logical design rule checks. The report lists the following:
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The Map Report (.mrp) contains warning and error messages
detailing logic optimization and problems in mapping logic to
physical resources. The report lists the following information:
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Note: The Map Report can be very large. To find information, use key
word searches. To quickly locate major sections, search for the string
‘---‘ , because each section heading is underlined with dashes.
The Place and Route Report (.par) contains the following
information.
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Missing or untranslatable hierarchical blocks
Invalid or incomplete timing constraints
Output contention, loadless outputs, and sourceless inputs
Erroneously removed logic. Sourceless and loadless signals can
cause a whole chain of logic to be removed. Each deleted element
is listed with progressive indentation, so the origins of removed
logic sections are easily identifiable; their deletion statements are
not indented.
Logic that has been added or expanded to optimize speed.
The Design Summary section lists the number and percentage of
used CLBs, IOBs, flip-flops, and latches. It also lists occurrences
of architecturally-specific resources like global buffers and
boundary scan logic.
The overall placer score which measures the “goodness” of the
placement. Lower is better. The score is strongly dependent on
the nature of the design and the physical part that is being
targeted, so meaningful score comparisons can only be made
between iterations of the same design targeted for the same part.
Xilinx Development System