DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 50

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
2-18
Specialized Simulation Controls
HDL Behavioral Simulation Capabilities
timing requirements. It creates timing analysis reports that you
customize by applying filters. It organizes and displays data that
allows you to analyze the critical paths in your circuit, the cycle time
of the circuit, the delay along any specified paths, and the paths with
the greatest delay. It also provide a quick analysis of the effect of
different speed grades on the same design.
Typically, the Simulation and Verification functions are invoked from
the project flowchart buttons. You can access the following individual
functions from the Project Manager toolbar, if needed.
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Foundation Series 2.1i allows you to add HDL behavioral simulation
capabilities to all design flows. HDL simulators from Aldec, Incorpo-
rated, and from MTI can be added to your Xilinx software. Sale and
support for Aldec’s ACTIVE-VHDL Behavioral Simulator and for
MTI’s ModelSim product are handled directly by those vendors.
Gate Simulator
When you select Tools
Gate Simulator from the Project Manager toolbar, you access
three startup options for the simulator.
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Checkpoint Gate Simulation Control
Checkpoint simulation pulls simulation data from the current
stage of the design database. If you want to select which netlist
(hierarchical or flat NGA netlist) to use for timing simulation,
you can access the Checkpoint Gate Simulation Control dialog by
selecting Tools
point Gate Simulation Control on the Project Manager
toolbar.
Opening the simulator with the netlist from the currently
open Foundation project
Selecting the netlist manually
Opening the simulator without loading a netlist
Simulation/Verification
Simulation/Verification
Xilinx Development System
Check-