DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 247

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Post Implementation Static Timing Analysis
Summary Timing Reports
The Timing Analyzer verifies that the delay along a given path or
paths meets your specified timing requirements. It organizes and
displays data that allows you to analyze the critical paths in a circuit,
the cycle time of the circuit, the delay along any specified path, and
the paths with the greatest delay. It also provides a quick analysis of
the effect of different speed grades on the same design.
The Timing Analyzer works with synchronous systems composed of
flip-flops and combinatorial logic. In synchronous designs, the
Timing Analyzer takes into account all path delays, including clock-
to-Q and setup requirements while calculating the worst-case timing
of the design. However, the Timing Analyzer does not perform setup
and hold checks. You must use a simulation tool for these checks.
The Timing Analyzer creates timing analysis reports, which you
customize by applying filters with the Path Filters menu commands.
For a complete description of the Timing Analyzer, see the Timing
Analyzer Guide, an online manual.
Post-implementation timing reports incorporate all delays to provide
a comprehensive timing summary. If an implemented design has met
all of your timing constraints, then you can proceed by creating
configuration data and downloading a device. On the other hand, if
you identify problems in the timing reports, you can try fixing the
problems by increasing the placer effort level or using re-entrant
routing. You can also redesign the logic paths to use fewer levels of
logic, tag the paths for specialized routing resources, move to a faster
device, or allocate more time for the paths.
Edit the Implementation template (from the Project Manager, select
Implementation
level. For information on re-entrant routing, see the “Running Re-
Entrant Routing on FPGAs” section in the “An Introduction to
Design Implementation chapter.
Summary reports show timing constraint performance and clock
performance. Implementing a design in the Flow Engine can
automatically generate summary timing reports. To create summary
timing reports, perform the following steps.
Options) to modify the Place & Route effort
Verification and Programming
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