DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 300

no-image

DS-FND-BSX-PC

Manufacturer Part Number
DS-FND-BSX-PC
Description
FOUNDATION BASE SYS W/SYN EXPRES
Manufacturer
Xilinx Inc
Type
Foundation Systemr
Datasheet

Specifications of DS-FND-BSX-PC

For Use With/related Products
Xilinx Programmable Logic Devices
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1185
Foundation Series 2.1i User Guide
B-28
Miscellaneous Examples
INST io_buf_instance_name LOC = P110 ;
NET io_net_name LOC = P111 ;
INST instance_path/BEL_inst_name LOC = CLB_R17C36 ;
CONFIG PROHIBIT = C26 ;
CONFIG PROHIBIT = CLB_R5C3 ;
INST obuf_instance_name FAST ;
INST obuf_instance_name SLOW ;
NET any_net_name MAXSKEW = 7 ;
NET any_net_name MAXDELAY = 20 ns;
Note: MEDDELAY/NODELAY can be attached to a CLB FF that is
pushed into an IOB by the “map -pr i” option.
INST input_ff_instance_name MEDDELAY ;
INST input_ff_instance_name NODELAY ;
Highest
See the on-line documentation set for additional timespec features or
additional information.
Assign an IO pin number or place a basic element (BEL) in a
specific CLB. BEL = FF, LUT, RAM, etc...
Prohibit IO pin C26 or CLB_R5C3 from being used.
Assign an OBUF to be FAST or SLOW.
Constrain the skew or delay associate with a net.
Declare an IOB input FF delay (default = MAXDELAY).
Also, constraint priority in your .ucf file is as follows.
1. Timing Ignore (TIG)
2. FROM : THRU : TO specs
3. FROM : TO specs lowest
4. OFFSET
5. PERIOD specs
Xilinx Development System

Related parts for DS-FND-BSX-PC