DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 230

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
11-24
Translate
MAP (FPGAs)
Place and Route (FPGAs)
The Flow Engine’s first step, Translate, merges all of the input
netlists. This is accomplished by running NGDBuild. For a complete
description of NGDBuild, refer to the “NGDBuild” chapter of the
Development System Reference Guide.
The MAP program maps a logical design to a Xilinx FPGA. The input
to a mapping program is an NGD file, which contains a logical
description of the design in terms of both the hierarchical
components used to develop the design and the lower level Xilinx
primitives, and any number of NMC (macro library) files, each of
which contains the definition of a physical macro. MAP first
performs a logical DRC (Design Rule Check) on the design in the
NGD file. MAP then maps the logic to the components (logic cells, I/
O cells, and other components) in the target Xilinx FPGA. The output
design is an NCD (Native Circuit Description) file physically
representing the design mapped to the components in the Xilinx
FPGA. The NCD file can then be placed and routed.
You can run the Mapper from a GUI (Flow Engine) or command line.
For a description of the GUI, see the Design Manager/Flow Engine
Guide, an online book. For a description of the MAP command and its
options, see the Development System Reference Guide, an online book.
After an FPGA design has undergone the necessary translation to
bring it into the NCD (Native Circuit Description) format, it is ready
to place and route. This phase is done by PAR (Xilinx's Place and
Route program). PAR takes an NCD file, places and routes the design,
and produces an NCD file, which is used by the bitstream generator
(BitGen). The output NCD file can also act as a guide file when you
place and route the design again after you make minor changes to it.
In the Xilinx Development System, PAR places and routes a design
using a combination of two methods.
•
Cost-based — This means that placement and routing are
performed using various cost tables which assign weighted
values to relevant factors such as constraints, length of
connection and available routing resources.
Xilinx Development System