ADV7125 Analog Devices, ADV7125 Datasheet

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ADV7125

Manufacturer Part Number
ADV7125
Description
330MHz Triple 8-Bit High Speed Video DAC
Manufacturer
Analog Devices
Datasheet

Specifications of ADV7125

Resolution (bits)
8bit
Dac Update Rate
330MSPS
Dac Settling Time
n/a
Max Pos Supply (v)
+5.25V
Single-supply
No
Dac Type
Current Out
Dac Input Format
Par

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FEATURES
330 MSPS throughput rate
Triple 8-bit DACs
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal Reference (1.235 V)
Single-supply +5 V/+3.3 V operation
48-lead LQFP and LFCSP packages
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) packages
Qualified for automotive applications
APPLICATIONS
Digital video systems
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
Automotive infotainment units
GENERAL DESCRIPTION
The ADV7125 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 8-bit video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7125 has three separate 8-bit-wide input ports. A
single +5 V/+3.3 V power supply and clock are all that are
required to make the part functional. The ADV7125 has
additional video control signals, composite SYNC and BLANK ,
as well as a power save mode.
ADV is a registered trademark of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Triple 8-Bit High Speed Video DAC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The ADV7125 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7125 is available in
48-lead LQFP and 48-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1.
2.
3.
G7 TO G0
R7 TO R0
B7 TO B0
CLOCK
BLANK
PSAVE
SYNC
330 MSPS (3.3 V only) throughput.
Guaranteed monotonic to eight bits.
Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
8
8
8
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
REGISTER
REGISTER
REGISTER
V
GND
©2002–2011 Analog Devices, Inc. All rights reserved.
AA
MODE
DATA
DATA
DATA
R
Figure 1.
8
8
8
SET
CMOS, 330 MHz
COMP
DAC
DAC
DAC
REFERENCE
VOLTAGE
CIRCUIT
SYNC LOGIC
BLANK AND
ADV7125
ADV7125
www.analog.com
IOR
IOR
IOG
IOG
IOB
IOB
V
REF

Related parts for ADV7125

ADV7125 Summary of contents

Page 1

... POWER-DOWN PSAVE MODE CLOCK GND R SET Figure 1. The ADV7125 is fabricated CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7125 is available in 48-lead LQFP and 48-lead LFCSP packages. PRODUCT HIGHLIGHTS 1. 330 MSPS (3.3 V only) throughput. 2. Guaranteed monotonic to eight bits. ...

Page 2

... ADV7125 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... Electrical Characteristics...................................................... 3 3.3 V Electrical Characteristics................................................... Timing Specifications ........................................................... 5 3.3 V Timing Specifications ........................................................ 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology .................................................................................... 10 REVISION HISTORY 2/11—Rev Rev. C Change to Table 6 ............................................................................. 8 7/10— ...

Page 3

... Green DAC, SYNC = high RGB DAC, SYNC = low OUT Tested with DAC output = 0 V FSR = 18. MHz CLK f = 140 MHz CLK f = 240 MHz CLK R = 530 Ω SET R = 4933 Ω SET PSAVE = low, digital, and control inputs ADV7125 DD ...

Page 4

... ADV7125 3.3 V ELECTRICAL CHARACTERISTICS 1.235 REF SET Table 2. 2 Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage Input Low Voltage Input Current PSAVE Pull-Up Current Input Capacitance, C ...

Page 5

... and for both 5 V and 3.3 V supplies Rev Page ADV7125 2 , unless otherwise noted 110°C. J MAX Unit Conditions MHz 50 MHz grade MHz 140 MHz grade MHz 240 MHz grade ...

Page 6

... ADV7125 3.3 V TIMING SPECIFICATIONS 3 3 1.235 REF SET Table 4. 3 Parameter ANALOG OUTPUTS Analog Output Delay, 4 Analog Output Rise/Fall Time 5 Analog Output Transition Time 6 Analog Output Skew CLOCK CONTROL 7 CLOCK Frequency 6 Data and Control Setup 6 Data and Control Hold ...

Page 7

... GND − 0 0.5 V section of this specification is not implied. Exposure to absolute AA −40°C to +85°C maximum rating conditions for extended periods may affect −65°C to +150°C device reliability. 150°C 300°C ESD CAUTION 220° Rev Page ADV7125 ...

Page 8

... TOP VIEW G4 7 (Not to Scale BLANK 11 SYNC 12 NOTES 1. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. Figure 3. Pin Configuration pins on the ADV7125 must be connected. AA Rev Page REF 35 COMP IOR 34 33 IOR 32 IOG 31 IOG ...

Page 9

... The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied permanently low. 38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is active. 49 (EPAD) EP (EPAD) The LFCSP_VQ has an exposed paddle that must be connected to GND. ...

Page 10

... ADV7125 TERMINOLOGY Blanking Level The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch IRE units the level that shuts off the picture tube, resulting in the blackest possible picture. ...

Page 11

... Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz The required CLOCK frequency is thus 78.6 MHz. All video data and control inputs are latched into the ADV7125 on the rising edge of CLOCK, as previously described in the Digital Inputs section recommended that the CLOCK input to the ADV7125 be driven by a TTL buffer (for example, the 74F244) ...

Page 12

... IOG (mA) = 11,444.8 × V (V)/R REF IOR, IOB (mA) = 7989.6 × V (V)/R REF Equation 1 applies to the ADV7125 only, when SYNC is being used. If SYNC is not being encoded onto the green channel, Equation 1 is similar to Equation 2. Using a variable value of R allows for accurate adjustment of SET the analog output video levels. Use of a fixed 560 Ω R yields the analog output levels quoted in the Specifications section ...

Page 13

... PCB. Alternatively, consideration can be given to using a 3- terminal voltage regulator. DIGITAL SIGNAL INTERCONNECT Isolate the digital signal lines to the ADV7125 as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7125 should be avoided to minimize noise pickup ...

Page 14

... For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7125 to minimize reflections. Additional information on PCB design is available in the AN-333 Application Note, Design and Layout of a Video Graphics System for Reduced EMI, which is available from Analog Devices at www ...

Page 15

... Dimensions shown in millimeters Rev Page 9.20 9. PIN 1 7.20 TOP VIEW 7.00 SQ (PINS DOWN) 6. 0.27 0.22 0.17 0.30 0.23 0.18 PIN 1 INDICATOR 48 1 EXPOSED 5.25 PAD 5.10 SQ (BOTTOM VIEW) 4. 0.25 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ADV7125 ...

Page 16

... ADV7125JSTZ330 is available in a 3.3 V option only. AUTOMOTIVE PRODUCTS The ADV7125W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications ...

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