NG80960JA-16 INTEL [Intel Corporation], NG80960JA-16 Datasheet
NG80960JA-16
Related parts for NG80960JA-16
NG80960JA-16 Summary of contents
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V EMBEDDED 32-BIT MICROPROCESSOR Product Features Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture —One Instruction/Clock Execution —Core Clock Rate is: 80960JA/JF 1x the Bus Clock 80960JD 2x the Bus Clock 80960JT 3x the Bus Clock —Load/Store ...
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V Microprocessor Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms ...
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Introduction .................................................................................................................. 7 2.0 80960Jx Overview 2.1 80960 Processor Core .......................................................................................... 9 2.2 Burst Bus.............................................................................................................10 2.3 Timer Unit............................................................................................................10 2.4 Priority Interrupt Controller ..................................................................................10 2.5 Instruction Set Summary .....................................................................................11 2.6 Faults and Debugging .........................................................................................11 2.7 Low Power Operation..........................................................................................11 2.8 Test ...
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V Microprocessor Figures 1 80960Jx Microprocessor Package Options...........................................................7 2 80960Jx Block Diagram ........................................................................................9 3 132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22 4 132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23 5 132-Lead ...
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Tables 1 80960Jx Instruction Set.......................................................................................13 2 Pin Description Nomenclature.............................................................................16 3 Pin Description — External Bus Signals .............................................................17 4 Pin Description — Processor Control Signals, Test Signals and Power .............20 5 Pin Description — Interrupt Unit Signals .............................................................21 6 132-Lead PGA ...
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Introduction This document contains information for the 80960Jx microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions — other than parametric performance — are published in the i960 (272483). Figure 1. 80960Jx Microprocessor Package Options i A80960JX ...
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V Microprocessor The 80960Jx rapidly allocates and deallocates local register sets during context switches. The processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. ...
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Figure 2. 80960Jx Block Diagram CLKIN PLL, Clocks, Power Mgmt TAP Boundary Scan Controller 5 8-Set Local Register Cache 128 Global / Local Register File SRC1 SRC2 DEST 3 Independent 32-Bit SRC1, SRC2, and DEST Buses 2.1 80960 Processor Core ...
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V Microprocessor 2.2 Burst Bus A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory and peripherals. The BCU fetches instructions and transfers data at the rate four 32-bit words per six ...
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Instruction Set Summary The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are: • Conditional Move • Conditional Add • Conditional Subtract • Byte Swap • Halt • Cache Control • Interrupt Control Table ...
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V Microprocessor 2.8 Test Features The 80960Jx incorporates numerous features which enhance the user’s ability to test both the processor and the system to which it is attached. These features include ONCE (On-Circuit Emulation) mode and Boundary Scan ...
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Table 1. 80960Jx Instruction Set Data Movement Load Store Move *Conditional Select Load Address Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls Mark Force Mark Asterisk (*) denotes new ...
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... NG80960JD-40 (40 MHz core, 20 MHz bus) • NG80960JD-33 (33 MHz core, 16 MHz bus) • NG80960JA/JF-33 (33 MHz) • NG80960JA/JF-25 (25 MHz) • NG80960JA/JF-16 (16 MHz) An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation 3.3 V ± 0.15 V over a case temperature range of -40° to 100°C: CC • TG80960JA-25 (25 MHz 3.3 V ± ...
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The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C: CC • GD80960JT-100 (100 MHz core, 33 MHz bus) • ...
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V Microprocessor 3.1 Pin Descriptions This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA) package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid Array (MPBGA). Section 3.1.1, ...
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Table 3. Pin Description — External Bus Signals (Sheet NAME TYPE I/O S(L) AD31:0 R(X) H(Z) P(Q) O R(0) ALE H(Z) P(0) O R(1) ALE H(Z) P(1) O R(1) ADS H(Z) P(1) O R(X) A3:2 H(Z) P(Q) ...
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V Microprocessor Table 3. Pin Description — External Bus Signals (Sheet NAME TYPE O R(1) BE3:0 H(Z) P(1) O WIDTH/ R(0) HLTD1:0 H(Z) P(1) O R(X) D/C H(Z) P(Q) O R(0) W/R H(Z) P(Q) O ...
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Table 3. Pin Description — External Bus Signals (Sheet NAME TYPE O R(1) BLAST H(Z) P(1) I RDYRCV S(L) I/O S(L) LOCK/ R(H) ONCE H(Z) P(1) I HOLD S(L) O R(Q) HOLDA H(1) P(Q) O R(0) BSTAT ...
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V Microprocessor Table 4. Pin Description — Processor Control Signals, Test Signals and Power NAME TYPE CLKIN I I RESET A(L) I STEST S(L) O R(0) FAIL H(Q) P(1) TCK I I TDI S(L) O R(Q) TDO HQ) ...
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Table 5. Pin Description — Interrupt Unit Signals NAME TYPE I XINT7:0 A(E/L) I NMI A(E) Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor DESCRIPTION EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0 pins can be configured in ...
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V Microprocessor 3.1.2 80960Jx 132-Lead PGA Pinout Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing AD25 AD22 N AD27 AD26 M AD30 AD29 L BE2 BE3 ...
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Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down AD6 AD11 AD13 N AD3 AD7 AD10 M AD0 AD4 L V AD1 CLKIN V ...
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V Microprocessor Table 6. 132-Lead PGA Pinout — In Signal Order Signal Pin AD0 M14 AD1 L13 AD2 K12 AD3 N14 AD4 M13 AD5 L12 AD6 P14 AD7 N13 AD8 M12 AD9 M11 AD10 ...
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Table 7. 132-Lead PGA Pinout — In Pin Order Pin Signal A1 ADS A2 WIDTH/HLTD1 A3 ALE A10 NMI A11 XINT7 A12 XINT5 A13 ...
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V Microprocessor 3.1.3 80960Jx 132-Lead PQFP Pinout Figure 5. 132-Lead PQFP - Top View 1 TRST TCK 2 TMS 3 HOLD 4 XINT0 5 XINT1 6 XINT2 7 XINT3 8 V (I/ (I/O) SS ...
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Table 8. 132-Lead PQFP Pinout — In Signal Order Signal Pin AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 100 AD7 101 AD6 102 ...
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V Microprocessor Table 9. 132-Lead PQFP Pinout — In Pin Order Pin Signal 1 TRST 2 TCK 3 TMS 4 HOLD 5 XINT0 6 XINT1 7 XINT2 8 XINT3 9 V (I/ (I/ ...
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MPBGA Pinout Figure 6. 196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing AD28 B V AD30 AD31 ...
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V Microprocessor Figure 7. 196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down AD8 B AD4 AD7 C AD2 AD6 D AD1 AD0 VCCPLL V G ...
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Table 10. 196-Ball MPBGA Pinout — In Signal Order (Sheet Signal Pin AD0 D13 AD1 D14 AD2 C14 AD3 D11 AD4 B14 AD5 D12 AD6 C13 AD7 B13 AD8 A13 AD9 B12 AD10 ...
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V Microprocessor Table 10. 196-Ball MPBGA Pinout — In Signal Order (Sheet Signal Pin VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VSS H4 VSS H5 VSS H6 VSS H7 VSS H8 VSS ...
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Table 11. 196-Ball MPBGA Pinout — In Pin Order (Sheet Pin Signal AD28 AD22 AD18 A10 AD15 A11 ...
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V Microprocessor Table 11. 196-Ball MPBGA Pinout — In Pin Order (Sheet Pin Signal L13 NC L14 RDYRCV M1 DT ALE M8 ...
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Table 12. 132-Lead PGA Package Thermal Characteristics Parameter (Junction-to-Case) JC (Case-to-Ambient) (No Heatsink) CA (Case-to-Ambient) (Omnidirectional Heatsink) CA (Case-to-Ambient) (Unidirectional Heatsink) CA NOTES: 1. This table applies to a PGA device plugged into a socket or soldered directly into a ...
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V Microprocessor Table 14. 132-Lead PQFP Package Thermal Characteristics Parameter (Junction-to-Case) JC (Case-to-Ambient -No Heatsink) CA NOTES: 1. This table applies to a PQFP device soldered directly into board 13°C/W ...
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... Table 17. Maximum T at Various Airflows in °C (80960JA/JF) A For NG80960JA/JF T without Heatsink A PQFP Package ...
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V Microprocessor 3.3 Thermal Management Accessories The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an endorsement or a warranty of the performance of any of the listed products and/or companies. 3.3.1 ...
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Electrical Specifications 4.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” ...
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V Microprocessor 4.3 Connection Recommendations For clean on-chip power distribution, V Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board, every V pin should connect to a power plane ...
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VCCPLL Pin Requirements To reduce clock skew on the i960 80960Jx processor, the VCCPLL pin for the Phase Lock Loop (PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise induced clock ...
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V Microprocessor 4.6 DC Specifications Table 21. 80960Jx DC Characteristics Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Output Ground Bounce OLP Input ...
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Table 22. 80960Jx I Characteristics (Sheet Symbol I Active CC (Thermal) I Test CC (Power modes) I Current on the CC5 VCC5 Pin NOTES: 1. These pins have internal pullup devices. Typical leakage current is not ...
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V Microprocessor 4.7 AC Specifications The 80960Jx AC timings are based upon device characterization. Table 23. 80960Jx AC Characteristics (Sheet Symbol CLKIN Frequency 80960JT-100 80960JT-75 80960JD-66 80960JD- 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 CLKIN ...
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Table 23. 80960Jx AC Characteristics (Sheet Symbol Input Setup to CLKIN — AD31:0, NMI, XINT7:0 T 80960JT IS1 80960JD 80960JA/JF Input Hold from CLKIN — AD31:0, NMI, XINT7:0 T 80960JT IH1 80960JD 80960JA/JF Input Setup to CLKIN ...
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V Microprocessor Table 23. 80960Jx AC Characteristics (Sheet Symbol T Input Setup to TCK — TDI, TMS BSIS1 T Input Hold from TCK — TDI, TMS BSIH1 T TDO Valid Delay BSOV1 T TDO Float ...
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Table 24. Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44) NOTES: 1. Not tested ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have ...
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V Microprocessor Figure 11. Output Delay or Hold vs. Load Capacitance nom + 7 nom + 6 nom + 5 nom + 4 nom + 3 nom + 2 nom + 1 nom + 0 Rise and Fall ...
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Figure 13. 80960JA/JF I Active (Power Supply) vs. Frequency CC Figure 14. 80960JA/JF I Active (Thermal) vs. Frequency CC 300 250 200 150 100 50 0 Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor Icc Active (Power Supply) vs Frequency 350 ...
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V Microprocessor Figure 15. 80960JD I Active (Power Supply) vs. Frequency CC Figure 16. 80960JD I Active (Thermal) vs. Frequency CC 600 500 400 300 200 100 Icc Active (Power Supply) vs. Frequency 600 500 ...
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Figure 17. 80960JT I Active (Power Supply) vs. Frequency CC Figure 18. 80960JT I Active (Thermal) vs. Frequency CC Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor Icc Active (Power Supply) vs. Frequency 600 500 400 300 200 100 0 15 ...
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V Microprocessor 4.7.2 AC Timing Waveforms Figure 19. CLKIN Waveform Figure 20. T Output Delay Waveform OV1 ALE (active), ALE (active), WIDTH/HLTD1:0, D/C, W/R, DEN, BLAST, LOCK, HOLDA, BSTAT, FAIL ...
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Figure 21. T Output Float Waveform OF WIDTH/HLTD1:0, D/C, W/R, DT/R, DEN, BLAST, LOCK Figure 22. T and T Input Setup and Hold Waveform IS1 IH1 CLKIN AD31:0 NMI XINT7:0 Figure 23. T and T Input Setup and Hold Waveform ...
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V Microprocessor Figure 24. T and T Input Setup and Hold Waveform IS3 IH3 CLKIN RESET Figure 25. T and T Input Setup and Hold Waveform IS4 IH4 RESET ONCE, STEST 54 1.5V 1. IH3 IS3 ...
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Figure 26 and T LX LXL LXA CLKIN AD31:0 Figure 27. DT/R and DEN Timings Waveform CLKIN DT/R DEN Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor Relative Timings Waveform T a 1.5V T LXL ALE 1.5V Valid ...
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V Microprocessor Figure 28. TCK Waveform Figure 29. T and T BSIS1 BSIH1 TCK TMS TDI Figure 30. T and T BSOV1 BSOF1 TCK TDO BSCR BSCF T BSCH Input Setup and Hold Waveforms 1.5V ...
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Figure 31. T and T BSOV2 BSOF2 TCK Non-Test Outputs Figure 32. T and T BSIS2 BSIH2 TCK Non-Test Inputs Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor Output Delay and Output Float Waveform 1.5V 1.5V T BSOV2 Valid 1.5V Input ...
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V Microprocessor 5.0 Bus Functional Waveforms Figure 33 through Figure 38 illustrate typical 80960Jx bus transactions. Figure 39 depicts the bus arbitration sequence. Figure 40 illustrates the processor reset sequence from the time power is applied to the ...
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Figure 34. Burst Read and Write Transactions Without Wait States, 32-Bit Bus CLKIN AD31:0 ALE ADS A3:2 BE3:0 WIDTH1:0 D/C W/R BLAST DT/R DEN RDYRCV Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor ...
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V Microprocessor Figure 35. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus CLKIN AD31:0 ALE ADS A3:2 BE3:0 WIDTH1:0 D/C W/R BLAST DT/R DEN RDYRCV ...
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Figure 36. Burst Read and Write Transactions Without Wait States, 8-Bit Bus CLKIN AD31:0 ALE ADS A3:2 BE1/A1 BE0/A0 WIDTH1:0 D/C W/R BLAST DT/R DEN RDYRCV Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor ...
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V Microprocessor Figure 37. Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read, 16-Bit Bus CLKIN AD31:0 ALE ADS A3:2 BE1/A1 BE3/BHE BE0/BLE WIDTH1:0 D/C W/R BLAST DT/R DEN RDYRCV 62 ...
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Figure 38. Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian CLKIN AD31:0 ALE ADS A3:2 BE3:0 WIDTH1:0 D/C W/R BLAST DT/R DEN RDYRCV Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor T T ...
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V Microprocessor Figure 39. HOLD/HOLDA Waveform For Bus Arbitration CLKIN Outputs: AD31:0, ALE, ALE, ADS, A3:2, BE3:0, WIDTH/HLTD1:0, D/C, W/R, DT/R, DEN, BLAST, LOCK HOLD HOLDA NOTE: HOLD is sampled on the rising edge of CLKIN. The processor ...
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Figure 40. Cold Reset Waveform ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ...
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V Microprocessor Figure 41. Warm Reset Waveform ~ ~ ~ ~ ~ ~ ~ ~ ...
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Figure 42. Entering the ONCE State ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor ~ ~ ~ ~ ~ ~ ~ ~ ~ ...
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V Microprocessor 5.1 Basic Bus States The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold (Th). During system operation, the processor continuously enters and exits different bus states. The bus ...
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Boundary-Scan Register The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins. Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that contain ...
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V Microprocessor Table 26. Natural Boundaries for Load and Store Accesses Data Width Double Word Table 27. Summary of Byte Load and Store Accesses Address Offset from Natural Boundary (in Bytes) +0 (aligned) Table 28. Summary of Short ...
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Summary of n -Word Load and Store Accesses ( Table 29. Address Offset from Natural Boundary in Bytes +0 (aligned = = ...
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V Microprocessor Figure 44. Summary of Aligned and Unaligned Accesses (32-Bit Bus) 0 Byte Offset Word Offset 0 Short-Word Load/Store Word Load/Store Double-Word Load/Store Short Access (Aligned) Byte, Byte Accesses Short ...
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Figure 45. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) 0 Byte Offset 0 Word Offset Triple-Word Load/Store Quad-Word Load/Store Advance Information Datasheet 80960JA/JF/JD/JT 3.3 V Microprocessor One Three-Word Burst (Aligned) ...
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V Microprocessor 6.0 Device Identification 80960Jx processors may be identified electrically, according to device type and stepping (see Figure 46, and Table 31 through Table 36). Table 30 identifies the device type and stepping for all 5V, 80960Jx ...
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Table 31. Fields of 80960JT Device ID Field Version See Table 3.3 V device CC Product Type 000 100 (Indicates i960 CPU) Generation Type 0001 = J-series Model D DPCC D = Clock Multiplier (P) Product ...
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V Microprocessor Table 33. Fields of 80960JD Device ID Field Version See Table 3.3 V device device 00 0100 Product Type (Indicates i960 CPU) Generation Type 0001 = J-series D000C ...
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Table 35. Fields of 80960JA/JF Device ID Field Version See Table 3.3 V device device Product Type 00 0100 (Indicates i960 CPU) Generation Type 0001 = J-series Model 0000C C = Cache ...
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