PIC16F677-I/ML Microchip Technology, PIC16F677-I/ML Datasheet - Page 189

• Manufacturer Part Number: PIC16F677-I/ML
• Description: IC PIC MCU FLASH 2KX14 20QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F677-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 18
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINDVA1004 - DEVICE ADAPTER 8/14/20DIP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.12.3
An SSP Mask (SSPMSK) register is available in I
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a ‘don’t care’.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
REGISTER 13-3:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed
R/W-1
MSK7
2: In all other SSP modes, this bit has no effect.
SSP MASK REGISTER
through the SSPMSK register. The SSPEN bit of the SSPCON register should be zero when accessing
the SSPMSK register.
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit 0 is compared to SSPADD<0> to detect I
0 = The received address bit 0 is not used to detect I
2
C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
R/W-1
MSK6
SSPMSK: SSP MASK REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-1
MSK5
PIC16F631/677/685/687/689/690
2
C Slave mode, 10-bit Address
R/W-1
MSK4
2
C
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
R/W-1
MSK3
This register must be initiated prior to setting
SSPM<3:0> bits to select the I
10-bit address).
This register can only be accessed when the appropriate
mode is selected by bits (SSPM<3:0> of SSPCON).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
2
2
C address match
(2)
C address match
R/W-1
MSK2
2
2
C address match
C address match
x = Bit is unknown
R/W-1
MSK1
2
C Slave mode (7-bit or
DS41262D-page 187
MSK0
R/W-1
(2)
bit 0