PIC16F677-I/ML Microchip Technology, PIC16F677-I/ML Datasheet - Page 194

• Manufacturer Part Number: PIC16F677-I/ML
• Description: IC PIC MCU FLASH 2KX14 20QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F677-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 18
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINDVA1004 - DEVICE ADAPTER 8/14/20DIP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
FIGURE 13-12:
TABLE 13-4:
DS41262D-page 192
0Bh/8Bh/
10Bh/18Bh
0Ch
13h
14h
86h
93h
94h
8Ch
Legend:
Note
SSPCON
Addr
SDA
CKP
SCL
WR
1:
2:
3:
INTCON
PIR1
SSPBUF
SSPCON
TRISB
SSPMSK
SSPSTAT
PIE1
PIC16F687/PIC16F689/PIC16F690 only.
SSPMSK register (Register 13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001.
See Registers 13-2 and 13-3 for more details.
Maintain these bits clear.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the SSP module.
Name
REGISTERS ASSOCIATED WITH I
(2)
Synchronous Serial Port Receive Buffer/Transmit Register
TRISB7
CLOCK SYNCHRONIZATION TIMING
SMP
WCOL
MSK7
Bit 7
GIE
—
—
(3)
TRISB6
SSPOV
CKE
MSK6
PEIE
ADIF
ADIE
Bit 6
DX
(3)
TRISB5
SSPEN
MSK5
RCIE
RCIF
Bit 5
T0IE
D/A
Master device
asserts clock
TRISB4
MSK4
Bit 4
INTE
TXIF
TXIE
CKP
P
2
SSPM3
RABIE
SSPIE
SSPIF
MSK3
C™ OPERATION
Bit 3
—
S
Master device
deasserts clock
CCP1IF
CCP1IE
SSPM2
MSK2
Bit 2
T0IF
R/W
—
TMR2IF
TMR2IF
SSPM1
MSK1
INTF
Bit 1
UA
—
(1)
TMR1IF
TMR1IF
SSPM0
RABIF
MSK0
Bit 0
© 2007 Microchip Technology Inc.
BF
—
0000 000x
-000 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
1111 ----
1111 1111
POR, BOR
Value on
DX-1
0000 000x
-000 0000
0000 0000
-000 0000
uuuu uuuu
0000 0000
1111 ----
1111 1111
Value on
all other
Resets