DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet
DSPIC30F3010-20I/SP
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DSPIC30F3010-20I/SP Summary of contents
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... Rev. A0/A1 Silicon Errata The dsPIC30F3010/3011 (Rev. A0/A1) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70141 – “dsPIC30F3010/3011 Data Sheet” ...
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... Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 11. Quadrature Encoder Interface (QEI) Module The Index Pulse Reset mode of the QEI does not work properly when used along with count error detection ...
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... MAC class instructions not use the + = address modification not prefetch data from Y data space. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 2. Module: CPU – Instruction DAW.b The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed ...
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... Example 2 is demonstrated in Example 3. DS80216K-page 4 These instructions are identified in Table 1. Example 2 demonstrates one scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F3010/3011 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
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... For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 5. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported. When device ...
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... Module: Interrupt Controller – Sequential Interrupts When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap. The generic terms “Interrupt 1” and “Interrupt 2” are used to represent any two enabled dsPIC30F interrupts ...
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... When the Watchdog Timer expires, code execution will resume from the instruction immediately following the SLEEP instruction. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 9. Module: Output Compare in PWM Mode If the desired duty cycle is ‘0’ (OCxRS = 0), the module will generate a high level glitch ...
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... Module: Quadrature Encoder Interface The Index Pulse Reset mode of the QEI does not work properly when used along with count error detection. When counting upwards, the POSCNT register will increment one extra count after the index pulse is received. The extra count will generate a false count error interrupt ...
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... Up to 153. 500 ksps Up to 256. 300 ksps Work around None. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 5.0 kΩ 4.5V to 5.5V -40°C to +125°C 5.0 kΩ 3.0V to 5.5V -40°C to +125°C ...
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... Module: QEI Interrupt Generation The Quadrature Encoder Interface (QEI) module does not generate an interrupt when MAXCNT is set to 0xFFFF and the following events occur: 1. POSCNT underflows from 0x0000 to 0xFFFF. 2. POSCNT stops. 3. POSCNT overflows from 0xFFFF to 0x0000. This sequence of events occurs when the motor is running in one direction, which causes POSCNT to underflow to 0xFFFF ...
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... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 9 described above would apply to a dsPIC30F3010 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function call would ...
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... Work around 2: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing consumption of the device. Similarly, instead of ...
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... Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT ...
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... Module: I/O Port – Port Pin Multiplexed with IC1 If the user application enables the auto-baud feature in the UART module, the I/O pin multiplexed with the IC1 (Input Capture) pin cannot be used as a digital input. Work around None. 19. Module: ADC Offset Error When Using ...
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... Work around None. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 27. Module: I When the I I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication Start” to all devices on the I ...
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... APPENDIX A: REVISION HISTORY Revision A (11/2004) Original version of the document. Revision B (3/2005) Added silicon issues 4 (PLL) and 5 (Interrupt Controller – Sequential Interrupts). Revision C (4/2005) Added silicon issue 6 (Using OSC2/RC15 pin for Digital I/O). Revision D (2/2006) Added silicon issues 7 (32 kHz Low-Power Oscillator), ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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